Delay Fault Modeling, Test, and Diagnosis

随着集成电路速度和密度的增加，越来越多的电路因延迟故障而失效——制造缺陷导致电路以低于预期的速度运行。这样的电路要么不能使用，要么必须以较低的价格出售。延迟故障的行为是复杂的，传统的制造测试方法在检测延迟故障方面越来越无效。本研究通过建立一种新颖的现实时延故障模型来解决这一问题。该模型被用于开发故障仿真、自动制造测试生成和下一代集成电路诊断的强大技术。这项工作是与美国半导体制造商合作完成的。这些测试和诊断技术正被整合到一个最先进的软件系统中，并将在实际生产问题上进行测试。新的现实延迟故障模型考虑了电阻桥和电阻开路，工艺变化对互连、器件和缺陷参数的影响，以及互连寄生的影响。快速布局和寄生提取算法以及模型降阶技术正在开发中，以降低给定精度水平下的模型成本。该模型被封装在参数化静态时序分析引擎中，用于故障仿真、测试生成和诊断。基于约束的故障覆盖分析用于确定一组向量上的故障覆盖。总之，这些技术可以准确地预测故障覆盖，并实现基于扫描的CMOS逻辑电路非常高的延迟故障覆盖。

As integrated circuit speed and density increases, more circuits fail due to delay faults -- manufacturing defects that cause the circuit to operate at a speed slower than intended. Such circuits either cannot be used or must be sold at a lower price. The behavior of delay faults is complex, and traditional manufacturing test approaches are increasingly ineffective in detecting them. This research attacks this problem by developing a novel realistic delay fault model. This model is being used to develop powerful techniques for fault simulation, automatic manufacturing test generation, and diagnosis for next-generation integrated circuits. This work is being done in cooperation with U.S. semiconductor manufacturers. These test and diagnosis techniques are being integrated into a state-of-art software system and will be tested on real manufacturing problems.The new realistic delay fault model considers resistive bridges and opens, the impact of process variation on interconnect, device, and defect parameters, and the influence of interconnect parasitics. Fast layout and parasitic extraction algorithms, and model order reduction techniques are being developed to reduce model cost for a given accuracy level. The model is encapsulated in a parameterized static timing analysis engine for use in fault simulation, test generation and diagnosis. A constraint-based fault coverage analysis is used to determine fault coverage over a set of vectors. Together, these techniques can accurately predict fault coverage and achieve very high delay fault coverage for scan-based CMOS logic circuits.