Exploiting the Critical Path in the Design and Performance Analysis of Modern Processors

现代处理器日益增长的并行性带来的一个不良后果是，将限制执行速度的事件与可以容忍延迟的事件区分开来的难度大大增加。关键路径分析是集中设计精力的一种方法。本研究提出在微架构层面应用关键路径分析，以检测和消除执行瓶颈。本研究将从以下四个方面探讨关键路径的潜力：(1)对微建筑关键路径进行建模。主要任务是定义关键路径的模型，即微执行中的事件和依赖集，这些事件和依赖集将在依赖图中公开，关键路径将在依赖图上计算。(2)关键路径的高效跟踪。这项工作将开发一种在线算法，该算法将使用每个节点的最后到达边缘来计算模拟器中一次通过的关键路径。(3)硬件关键路径预测器。本研究将探讨近似方法的使用，以避免整个依赖图的分析。(4)临界感知处理器策略。本研究将使用硬件关键路径预测器将硬件策略集中在可能在关键路径上的事件上。

An undesired consequence of the growing parallelism of modern processors is that it is dramatically more difficult to separate the events that limit execution speed from the events whose latencies are tolerated. A method for focusing design effort is critical-path analysis. This research proposes to apply critical-path analysis at the micro-architectural level, with the goal of detecting and eliminating execution bottlenecks.This research will explore the potential of the critical path in four interrelated efforts: (1) Modeling the micro-architectural critical path. The main task is to define a model of the critical path, i.e., the set of events and dependences in a micro-execution that will be exposed in the dependence graph on which the critical pathwill be computed. (2) Efficient tracing of the critical path. This effort will develop an on-line algorithm that will use a last-arrival edge at each node to calculate the critical path in one pass in a simulator. (3) Hardware critical-path predictors. This research will explore the use of approximation methods in avoiding the analysis of the entire dependence graph. (4) Criticality-aware processor policies. This research willuse hardware critical-path predictors to focus hardware policies on events likely to be on the critical path.