ITR: Statically Speculative Power-Aware\(SPA)\Architectures

该项目主要关注支持编译器的节能体系结构。它的目的是以智能的方式利用静态程序信息，以降低嵌入式和通用体系结构中的功耗和能耗。我们遵循三个关键的总体思想来实现这一目标：(1)我们使用静态信息来节流处理器资源；(2)我们结合体系结构特征来直接支持静态编译器管理的操作模式；(3)除了可预测的静态信息之外，我们还利用推测的静态信息来支持(1)和(2)。我们已经在多个处理器体系结构领域证明了我们的方法是可行的，并且可以很容易地实现，并且可以实现比仅使用电路和体系结构技术所能实现的显著节能。我们估计，与最先进的低功耗设计相比，我们的技术如果结合在一起，可以额外节省30%或更多的能源，而不会显著影响性能。

This project focuses on compiler-enabled power-aware architectures. Its purpose is to leverage static program information in smart ways, to reduce power and energy consumption in both embedddedand general-purpose architectures.We follow three key general ideas to achieve this goal:(1) we use static information to throttle processor resources,(2) we incorporate architectural features to directly support staticcompiler managed modes of operation, and(3) we leverage speculative static information in addition tothe predictable static information to support (1) and (2). We have demonstrated, in a number of processor architectural domains, that our approach is feasible, and can be easily implemented, and that considerable energy savings, beyond what would be possible with circuitand architectural techniques alone, can be achieved.We estimate that our techniques if combined, can give an additional 30% or more energy savings compared to state-of-the-art low-power designs, while not significantly affecting performance.