Architecture Design Methodologies for Embedded Communications Terminals

对随时随地宽带接入的需求持续增长。虽然降低个人终端中的功耗是重要的，但是降低诸如机顶盒、中心局中的DSL调制解调器或无线基站之类的应用中的硅成本同样重要。该建议解决了许多个人或中央嵌入式通信终端所共有的许多关键构建块的低功率和/或低成本实现。 迭代译码器在无线终端、无线基础设施、卫星通信等领域有着广泛的应用。近年来，低密度奇偶校验（LDPC）编码器由于其每次迭代计算简单、并行化能力强而备受关注。这些代码不受错误平层问题的影响，非常适合于光传输和磁盘驱动器等应用。并行turbo解码器架构的早期工作将扩展到解决有效的存储器仲裁和存储器管理问题，并通过适当的并行度和存储器选择来降低功耗。也有兴趣在设计一类新的并行涡轮编码器，可以借给自己以及并行实现。在LDPC编码器的早期工作中，展示了一种新的（3，k）-正则LDPC码，其适合于部分并行实现。 拟议的努力将建立在过去的工作，以产生更一般的LDPC编码器。适应变化的速率、变化的帧大小的期望要求可以以部分并行方式实现的（j，k）-规则LDPC编码器的一般化或构造。放置和路由问题，这些编码器和内存大小减少的问题将得到解决。 该建议的智力价值在于联合考虑算法和架构问题以降低宽带系统的许多组件的功耗的独特能力。算法和架构级功耗降低可以显著节省成本和功耗。拟议的努力将对卫星通信、光通信、存储设备、个人录像机、机顶盒、无线基站和手机等各种应用产生影响。更广泛的影响将是深远的。这项研究将为这些技术在工业产品中的应用铺平道路。它将通过对从事该项目的学生进行研究培训产生影响，但通过将这些研究成果转移到新的或现有的研究生班，研究生教育的影响将更大。

Demand for broadband access anytime anywhere continues to grow. While it is important to reduce to power consumption in personal terminals, it is equally important to reduce silicon cost in applications such as settop boxes, DSL modems in central office or a wireless base stations. This proposal addresses low-power and/or low-cost implementations of a number of key building blocks which are common to many personal or central embedded communications terminals. Iterative decoders have found wide applications in wireless terminals, wireless infrastructure, satellite communications, etc. Recently, low-density parity check (LDPC) coders are receiving much attention due to their computation simplicity in every iteration, and ability to parallelize. These codes do not suffer from the error floor problem and are well suited for applications such as optical transmission and disk drives. Earlier work on parallel turbo decoder architectures will be extended to address efficient memory arbitration and memory management issues, and to reduce power consumption by appropriate parallelism level and memory selections. There is also interest in design of a new class of parallel turbo coders which can lend itself well for parallel implementations. In earlier work on LDPC coders, a new (3,k)-regular LDPC code which lends itself well for a partly-parallel implementations was demonstrated. The proposed effort will build upon this past work to generate more general LDPC coders. The desire to accommodate varying rates, varying frame sizes demands the generalization or construction otherwise of (j,k)-regular LDPC coders which can be implemented in partly-parallel manner. Placement and routing issues in these coders and memory size reduction issues will be addressed. The intellectual merit of this proposal lies in the unique ability to jointly consider algorithm and architectural issues to reduce power consumption of many components of broadband systems. Algorithm and architectural level power reduction can result in dramatic cost and power savings. The proposed effort will have an impact in various applications such as satellite communications, optical communications, storage devices, personal video recorders, settop boxes, wireless base stations and cell phones. The broader impacts will be far reaching. This research will pave the way for use of these technologies in industrial products. It will make an impact through research training of students working on this project, but the impact will be even greater through graduate education by transferring these research results to new or existing graduate classes.