ITR: Advanced Architectures and Technologies for Chip Multiprocessors

芯片多处理器的先进体系结构和技术摘要随着半导体技术使芯片多处理器（CMP）成为可能，我们正处于计算机性能的另一个不连续性的边缘，其中单个芯片包含通过共享存储器连接的多个处理元件。这些CMPs有可能大大降低成本，提高信息服务的可靠性，这些信息服务是社会商业、科学、教育和政府的基本基础设施的基础。本研究针对这种范式转变的潜在障碍，有三个重点：o令牌一致性协议来管理复杂性。Token Coherence寻求在一个新的基础上重建一致性，该基础通过以下方式更可验证：（a）将正确性与性能增强分离，以及（B）将正确性降低为安全机制（即，令牌）和活性和饥饿自由机制。传统的布线受到RC延迟的限制，这成为深亚微米半导体技术中的一个重要因素。我们将研究使用片上传输线来减少延迟并提高CMP的性能。o压缩缓存来减少片外带宽。CMP必须有效利用有限的片外带宽。我们将研究数据压缩技术，以减少每个缓存块传输的位数，并增加有效的片上缓存大小。

Advanced Architectures and Technologies for Chip MultiprocessorsAbstractWe are poised on the verge of another discontinuity in computer performance as semiconductor technology enables Chip Multiprocessors (CMPs), wherein a single chip contains multiple processing elements connected via shared memory. These CMPs have the potential to greatly decrease the cost and increase the reliability of the information services that underpin society's essential infrastructure for commerce, science, education, and government.This research targets potential barriers to this paradigm shift with three thrusts:o Token coherence protocols to manage complexity. Token Coherence seeks to rebuild coherence on a new foundation that is more verifiable by (a) separating correctness from performance enhancements and (b) reducing correctness to a mechanism for safety (namely, tokens) and a mechanism for liveness and starvation freedom.o On-chip transmission lines to reduce on-chip communication latency. Conventional wires are limited by RC delay, which becomes a significant factor in deep-submicron semiconductor technologies. We will investigate using on-chip transmission lines to reduce latency and improve performance in CMPs.o Compressed caches to reduce off-chip bandwidth. CMPs must make effective use of limited off-chip bandwidth. We will investigate data compression techniques to both transfer fewer bits per cache block and increase effective on-chip cache size.