ITR - (ASE) - (int): CAD for Reducing Soft Error Failure Rates in Logic Circuits

提案ID：0426608 PI：Touba，努尔组织：德克萨斯大学奥斯汀分校标题：ITR -（ASE）-（int）：降低逻辑电路软错误故障率的CAD 翻译后摘要：降低逻辑电路的软错误故障率是更昂贵和困难的存储器，预计将成为一个非常重要的问题，在未来的主流低成本电子技术的不断扩大。 目前，缺乏计算机辅助设计（CAD）工具和技术来以具有成本效益的方式解决这个问题。 该研究项目涉及开发一种新的范式，用于设计具有软错误保护的逻辑电路，以降低软错误故障率。 一个细粒度的定量方法将被调查的敏感性的逻辑电路软错误估计在设计过程中的每一步和容错功能被纳入需要在一个成本效益的方式，以满足软错误故障率的要求。 本研究的核心思想之一是利用逻辑电路内部节点的非对称软错误敏感性来指导容错功能的插入。 与每个单元中的软错误的概率相等的存储器不同，在逻辑电路中，在一些内部节点处的翻转可以具有比在其他节点处更大数量级的被锁存并导致软错误的概率。 通过将错误检测和/或错误掩蔽能力集中到最易受软错误影响的节点，逻辑电路中的软错误故障率可以以试图保证覆盖所有节点的现有技术的成本的一小部分而显著降低。 该项目的目标包括开发有效的程序，估计软错误的敏感性，开发CAD算法的成本效益插入容错功能，并开发软错误保护计划，尽量减少对时序和功耗的影响。

Proposal ID: 0426608 P I: Touba, Nur Organization: University of Texas at Austin Title: ITR - (ASE) - (int): CAD for Reducing Soft Error Failure Rates in Logic Circuits Abstract:Reducing the soft error failure rate for logic circuits is more expensive and difficult than for memories and is expected to emerge as a very important problem in the future for mainstream low-cost electronics as technology continues to scale. Currently, there is a lack of computer-aided design (CAD) tools and techniques for addressing this problem in a cost-effective manner. This research project involves developing a new paradigm for designing logic circuits with protection from soft errors to reduce the soft error failure rate. A fine-grain quantitative approach will be investigated where the susceptibility of the logic circuit to soft errors is estimated at each step of the design process and fault tolerance features are incorporated as needed in a cost effective way to satisfy soft error failure rate requirements. One of the key ideas in this research is to exploit the asymmetric soft error susceptibility of internal nodes in a logic circuit to direct the insertion of fault tolerance features. Unlike memories where the probability of a soft error in each cell is equally likely, in logic circuits upsets at some internal nodes can have orders of magnitude greater probability of being latched and causing a soft error than at other nodes. By focusing error detection and/or error masking capability towards the nodes that are most susceptible to soft errors, the soft error failure rate in logic circuits can be significantly reduced at a fraction of the cost of existing techniques which try to guarantee coverage of all nodes. The objectives of this project include developing efficient procedures for estimating soft error susceptibility, developing CAD algorithms for cost-effective insertion of fault tolerance features, and developing soft error protection schemes that minimize impact on timing and power.