A CAD Framework for Multiscale Electrothermal Modeling and Simulation of Non-Classical CMOS Devices

banerjee, KaustavU, calsanta barbara，非经典CMOS器件多尺度电热建模和仿真CAD框架随着CMOS器件在90 nm节点以上的扩展，包括严重的短通道效应、不断增加的泄漏电流和功耗在内的许多关键挑战正在加速新材料和器件结构的引入，以延长CMOS的使用寿命，甚至可能超过22 nm节点。这些器件被归类为非经典CMOS，包括应变硅、超薄体绝缘体硅（UTB-SOI）、双栅（如finfet）和多栅器件。虽然这些器件结构寻求解决上述缩放挑战，但由于引入导热性较差的材料（SOI, SiGe）和器件几何形状的物理限制，这些超大尺寸器件的热管理问题日益受到关注。此外，对于声子的平均自由程与器件尺寸（通道长度）相当（或大于）的器件几何形状，经典的漂移扩散理论无法准确预测晶体管通道区域的温度分布。目前，广泛用于器件级电热模拟的CAD工具使用漂移扩散或流体动力学模型和能量平衡方程，假设局部热力学平衡，因此没有考虑这些影响，从而损害了基于这些器件的集成电路的性能和可靠性。此外，目前还没有明确定义的方法来结合不同长度尺度的电热模型（如CMOS晶体管所需要的），并随后生成精确的紧凑模型，以允许快速的电热模拟。此外，在这些新兴的CMOS器件中缺乏热管理也会导致可靠性问题的显著增加，例如静电放电（ESD），这是半导体行业中所有IC故障的最大单一原因。因此，迫切需要开发合适的CAD框架来进行精确的多尺度电热建模和仿真，以了解热效应对这些非经典器件的电气特性以及随后对其电路性能和可靠性的影响。该框架对于优化这些器件的设计和理解各种电热权衡也至关重要。PI计划开发必要的CAD框架，以实现超尺度非经典CMOS器件的多尺度电热建模和仿真能力。该研究采用了一种独特的方法，将涉及电子-声子玻尔兹曼输运方程（BTE）的小尺度亚连续统电热模拟方法与基于宏观尺度热扩散的方法相结合。为了考虑在晶体管高电场（漏极）区域附近声子输运的非局域性，需要进行小规模的模拟，并涉及电子- bte和声子- bte的自一致解，以沿着器件的通道产生精确的热通量和热分布。接下来，通过将这些模拟结果与经典热扩散方法（用于晶体管的其他区域）的模拟结果耦合在一起，PI将为各种电热量（包括热阻、热电容和热时间常数，作为器件材料、工艺和偏置条件以及器件几何形状的函数）开发精确的物理和紧凑的模型。这些紧凑的模型将用于使用SPICE进行快速稳态和瞬态电热模拟，从而分析和优化各种晶体管架构。最重要的是，由于性能和功耗严重依赖于热剖面，因此电热CAD框架将用于设计热感知电路，以便从中获得最大效益，并可以进行各种电热权衡。此外，PI将研究ESD保护电路的影响，了解大电流条件下的电热行为，并优化器件设计以提高ESD可靠性。整个项目还通过参与由教育专业人士设计的项目，将研究与各级教育（K-12、本科、研究生、继续教育）联系起来。作为加州纳米系统研究所（CNSI）的附属学院，PI计划参加由CNSI以及UCSB材料研究实验室（MRL）和纳米技术（NNIN）提供的各种外展活动，包括学生和教师研究培训实习计划。此外，该项目提供了一个实质性的重点，招募和保留代表性不足的群体进入纳米科学和工程。

0541465Banerjee, KaustavU of Cal Santa BarbaraA CAD Framework for Multiscale Electrothermal Modeling and Simulation of Non-Classical CMOS DevicesAs scaling of CMOS devices continues unabated beyond the 90 nm node, a number of critical challenges including severe short-channel effects, increasing leakage currents and power dissipation are accelerating the introduction of new materials and device structures to extend the lifetime of CMOS down to, and perhaps beyond the 22 nm node. These devices are classified as non-classical CMOS and include strained-Si, ultra-thin body Silicon-on-Insulator (UTB-SOI), double-gate (such as FinFETs) and multi-gate devices. While these device structures seek to address the above mentioned scaling challenges, thermal management in these ultra scaled devices is an increasing concern made worse by the introduction of materials with poorer thermal conductivity (SOI, SiGe) and the physical confinement of the device geometries. Moreover, for device geometries where the mean free path of the phonons are comparable to (or larger than) the device size (channel length), classical drift-diffusion theory fails to accurately predict the temperature profile in the channel region of the transistors. At present, CAD tools that are widely used for device level electrothermal simulations, use drift-diffusion or hydrodynamic models and energy-balance equations assuming local thermodynamic equilibrium and therefore do not account for these effects, thereby compromising the performance and reliability of integrated circuits based on these devices. Moreover, there is no well defined methodology that combines electrothermal models at different length scales (as needed for a CMOS transistor) and subsequently generates accurate compact models to allow fast electrothermal simulations. Additionally, lack of thermal management in these emerging CMOS devices can also lead to significant increase in reliability problems such as electrostatic discharge (ESD), which is known to be the largest single cause of all IC failures in the semiconductor industry. Hence, there is an imminent need for developing suitable CAD framework for accurate multi-scale electrothermal modeling and simulation, in order to understand the impact of thermal effects on the electrical characteristics of these non-classical devices and subsequently on their circuit performance and reliability. The framework is also critical for optimizing the design of these devices and to understand various electrical-thermal tradeoffs.The PI plans to develop the necessary CAD framework to enable multi-scale electrothermal modeling and simulation capabilities for ultra-scaled non-classical CMOS devices. The research involves a unique approach that combines a small-scale sub-continuum electrothermal simulation methodology involving the electron-phonon Boltzmann Transport Equations (BTE) with a macro-scale heat-diffusion based methodology. The small-scale simulations are necessary to account for the non-locality of phonon transport near the high electric field (drain) region of the transistor and involve self-consistent solutions of the electron-BTE and the phonon-BTE to generate accurate heat flux and thermal profile along the channel of the device. Next, by coupling together the results of these simulations with the ones from classical heat-diffusion approach (for other areas of the transistors) the PI will develop accurate physical as well as compact models for various electrothermal quantities including thermal resistance, thermal capacitance and thermal time constant as a function of device materials, process and bias conditions, and device geometry. These compact models will then be used to carry out fast steady-state and transient electrothermal simulations using SPICE and thereby analyze and optimize various transistor architectures. Most importantly, since performance and power dissipation are critically dependent on the thermal profile, the electrothermal CAD framework will be used to design thermally-aware circuits so that maximum benefit can be derived from them and various electrical-thermal tradeoffs can be carried out. Additionally, the PI will study implications for ESD protection circuitsunderstand electrothermal behavior under high-current conditions and optimize device design for improving ESD reliability. The overall program also ties research to education at all levels (K-12, undergraduate, graduate, continuing-ed) partly via participation in programs designed by education professionals. As an affiliated faculty of the California NanoSystems Institute (CNSI), the PI plans to participate in various outreach activities sponsored by the CNSI as well as those offered by the Materials Research Lab (MRL) and the Nanotech (NNIN) at UCSB including the student and teacher research training internship programs. Additionally, the project provides a substantial focus on recruitment and retention of underrepresented groups into nanoscience and engineering.