NSF:EAGER: 2D Layered Heterostructure based Tunnel Field-Effect Transistors (TFETs) and Circuits

NSF：EAGER：基于 2D 分层异质结构的隧道场效应晶体管 (TFET) 和电路

• 批准号: 1550230
• 负责人: Kaustav Banerjee
• 金额: $ 17万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-09-01 至 2017-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1550230&HistoricalAwards=false
• 关键词: NSF; EAGER; 2D; Layered; Heterostructure

The global semiconductor/electronics industry is confronting a fundamental challenge in the form of increasing power and energy consumption by the complementary-metal-oxide-semiconductor (CMOS) switches that have been the workhorse of the electronics industry for over four decades. Band-to-band tunneling field-effect transistors (TFETs) are considered the most promising post-CMOS switches, since they provide abrupt switching characteristics, and thereby enable ultra-small supply voltage and switching energy without compromising the ON-OFF switching current ratio, which is un-achievable in conventional CMOS devices. However, in spite of major efforts around the world, it has been found extremely challenging to design a working TFET using conventional bulk materials such as silicon, germanium or III-V semiconductors, due to a number of limitations including their inability to be thinned down below some critical value (that is essential for increasing the energy-efficiency of transistors designed with those materials), without loss of essential properties, as well as due to the existence of large density of interface traps arising from the inherent dangling bonds that exist at the surfaces of all such covalently bonded materials. 2-dimensional (2D) layered materials are atomically-thin and have pristine surfaces, and can therefore overcome the limitations of bulk materials. The main goal of this project is to explore the feasibility of using such 2D materials such as molybdenum disulphide, to build a TFET that can meet the performance requirements of the semiconductor industry and thereby replace the CMOS as the next-generation ultra-low power and energy-efficient electronic switch. Such a transistor can potentially revolutionize the worldwide electronics and information technology (IT) industries and bring transformative changes to computing, sensing and many other areas that affect the way we live, work and play.Tunneling field-effect Transistors (TFETs) are considered the most promising post-CMOS switches, since they provide abrupt switching characteristics, i.e., small (60 mV/decade at room temperature) sub-threshold swing (SS), and hence enable ultra-small supply voltage and switching energy without compromising ON-OFF current ratio, which is un-achievable in conventional CMOS devices . However, it has been found extremely challenging to recover the expected TFET performance on bulk material platform, which results from 1) inefficient gate control leading to large tunnel barrier width and low ON-current; 2) large band gap leading to high tunnel barrier and low ON-current; 3) interface trap induced leakage current leading to large SS. Utilizing the emerging 2D materials for TFET application can potentially overcome these issues, because 2D materials have 1) sizable band gap and band alignment that allow staggered- or even broken-gap type heterojunction design and lowering of tunnel barrier height, 2) ultra-thin body that provides excellent gate control and hence lowers tunnel barrier width and 3) pristine surface that greatly suppresses the trap generation. Therefore, the goal of this project is to explore (both theoretically and via experiments) 2D materials based TFETs. More specifically, we propose to employ a 2D heterostructure material platform to design and fabricate the proposed TFET device, which is radically different from all previous efforts reported in literature. This project is expected to have wide implications for the semiconductor and IT industries. Broader impact of the proposed research is also well recognized, particularly in the light of 3D integration technology now being employed worldwide, where eventual integration of ultra-low leakage and relatively temperature insensitive TFETs could be exploited to build next-generation high-performance and ultra-low power integrated circuits to support Big Data applications such as Internet of Things, social media, etc. The overall program also ties research to education at all levels.

全球半导体/电子行业正面临着一项根本性的挑战，即40多年来一直是电子行业主力的互补金属氧化物半导体(CMOS)开关不断增加的功率和能源消耗。带到带隧道效应晶体管(TFET)被认为是最有前途的后CMOS开关，因为它们提供了突变的开关特性，从而在不影响开关电流比的情况下实现了超小的电源电压和开关能量，而这在传统的CMOS器件中是无法实现的。然而，尽管世界各地做出了重大努力，但人们发现，使用传统的体相材料如硅、锗或III-V半导体设计工作TFET具有极大的挑战性，这是因为它们存在一些限制，包括它们无法在不损失基本性能的情况下被稀释到某个临界值以下(这对于提高使用这些材料设计的晶体管的能效至关重要)，以及由于所有这些共价键合材料表面存在的固有悬挂键产生的高密度界面陷阱。二维(2D)层状材料是原子级的，具有原始的表面，因此可以克服块状材料的限制。该项目的主要目标是探索使用二硫化钼等2D材料的可行性，构建能够满足半导体行业性能要求的TFET，从而取代CMOS成为下一代超低功耗和高能效的电子开关。这种晶体管可能会给全球电子和信息技术(IT)产业带来革命性的变化，并给计算、传感和许多其他领域带来革命性的变化，影响我们的生活、工作和娱乐方式。隧道场效应晶体管(TFET)被认为是最有前途的后CMOS开关，因为它们提供了突变的开关特性，即很小的(室温下为60 mV/十)亚阈值摆幅(SS)，因此能够在不影响开关电流比的情况下实现超小的电源电压和开关能量，而这在传统的CMOS器件中是无法实现的。然而，在块状材料平台上恢复预期的TFET性能是非常困难的，这是由于1)低效的栅控导致较大的隧道势垒宽度和较低的导通电流；2)较大的带隙导致较高的隧道势垒和较低的导通电流；3)界面陷阱引起的泄漏电流导致较大的SS。将新兴的2D材料用于TFET应用可以潜在地克服这些问题，因为2D材料具有1)较大的带隙和能带对齐，允许交错甚至破碎带隙类型的异质结设计和降低隧道势垒高度，2)超薄的本体，提供出色的栅极控制，从而降低隧道势垒宽度，以及3)原始表面，极大地抑制陷阱的产生。因此，本项目的目标是探索(理论和实验)基于二维材料的TFET。更具体地说，我们建议使用2D异质结构材料平台来设计和制造所提出的TFET器件，这与以往文献中报道的所有努力都有根本的不同。这个项目预计将对半导体和IT行业产生广泛的影响。拟议研究的更广泛影响也得到了很好的认识，特别是鉴于目前全球正在采用3D集成技术，最终可以利用超低泄漏和相对温度不敏感的TFET的集成来构建下一代高性能和超低功耗集成电路，以支持物联网、社交媒体等大数据应用。