NSF:EAGER: 2D Layered Heterostructure based Tunnel Field-Effect Transistors (TFETs) and Circuits

四十多年来，互补金属氧化物半导体（CMOS）开关一直是电子工业的主力，而全球半导体/电子工业正面临着不断增加的功率和能源消耗的根本性挑战。带到带隧道场效应晶体管（tfet）被认为是最有前途的后CMOS开关，因为它们提供突然开关特性，从而实现超小的电源电压和开关能量，而不会影响传统CMOS器件无法实现的ON-OFF开关电流比。然而，尽管世界各地都做出了巨大的努力，但由于许多限制，包括它们无法减薄到某些临界值以下（这对于提高用这些材料设计的晶体管的能量效率至关重要），因此，使用传统的块状材料（如硅、锗或III-V半导体）设计一个工作的ttfet极具挑战性。此外，由于存在大密度的界面陷阱，这些陷阱是由存在于所有这些共价结合材料表面的固有悬空键引起的。二维（2D）层状材料具有原子厚度和原始表面，因此可以克服块状材料的局限性。该项目的主要目标是探索利用二硫化钼等二维材料，构建满足半导体行业性能要求的TFET，从而取代CMOS成为下一代超低功耗和节能电子开关的可行性。这种晶体管有可能彻底改变全球电子和信息技术（IT）行业，并给计算、传感和许多其他影响我们生活、工作和娱乐方式的领域带来革命性的变化。隧道场效应晶体管（tfet）被认为是最有前途的后CMOS开关，因为它们提供了突然开关特性，即小（室温下60 mV/ 10）亚阈值摆幅（SS），因此可以实现超小的电源电压和开关能量，而不会影响开关电流比，这在传统CMOS器件中是无法实现的。然而，在块状材料平台上恢复预期的ttfet性能是非常具有挑战性的，其原因是：1)栅极控制效率低下，导致隧道势垒宽度大，导通电流低；2)大带隙导致高隧道势垒和低导通电流；3)界面陷阱诱导泄漏电流导致大SS。利用新兴的2D材料用于ttfet应用可以潜在地克服这些问题，因为2D材料具有1)相当大的带隙和带对，允许交错或甚至断隙型异质结设计和降低隧道势垒高度，2)超薄的体提供了出色的栅极控制，因此降低了隧道势垒宽度，3)原始表面大大抑制了陷阱的产生。因此，这个项目的目标是探索（理论上和通过实验）基于二维材料的tfet。更具体地说，我们建议采用二维异质结构材料平台来设计和制造所提出的TFET器件，这与以往文献报道的所有努力有根本不同。预计该项目将对半导体和IT行业产生广泛的影响。所提出的研究的广泛影响也得到了很好的认可，特别是考虑到3D集成技术目前正在全球范围内使用，超低泄漏和相对温度不敏感的tfet的最终集成可以用来构建下一代高性能和超低功耗集成电路，以支持物联网，社交媒体等大数据应用。整个项目还将研究与各级教育联系起来。

The global semiconductor/electronics industry is confronting a fundamental challenge in the form of increasing power and energy consumption by the complementary-metal-oxide-semiconductor (CMOS) switches that have been the workhorse of the electronics industry for over four decades. Band-to-band tunneling field-effect transistors (TFETs) are considered the most promising post-CMOS switches, since they provide abrupt switching characteristics, and thereby enable ultra-small supply voltage and switching energy without compromising the ON-OFF switching current ratio, which is un-achievable in conventional CMOS devices. However, in spite of major efforts around the world, it has been found extremely challenging to design a working TFET using conventional bulk materials such as silicon, germanium or III-V semiconductors, due to a number of limitations including their inability to be thinned down below some critical value (that is essential for increasing the energy-efficiency of transistors designed with those materials), without loss of essential properties, as well as due to the existence of large density of interface traps arising from the inherent dangling bonds that exist at the surfaces of all such covalently bonded materials. 2-dimensional (2D) layered materials are atomically-thin and have pristine surfaces, and can therefore overcome the limitations of bulk materials. The main goal of this project is to explore the feasibility of using such 2D materials such as molybdenum disulphide, to build a TFET that can meet the performance requirements of the semiconductor industry and thereby replace the CMOS as the next-generation ultra-low power and energy-efficient electronic switch. Such a transistor can potentially revolutionize the worldwide electronics and information technology (IT) industries and bring transformative changes to computing, sensing and many other areas that affect the way we live, work and play.Tunneling field-effect Transistors (TFETs) are considered the most promising post-CMOS switches, since they provide abrupt switching characteristics, i.e., small (60 mV/decade at room temperature) sub-threshold swing (SS), and hence enable ultra-small supply voltage and switching energy without compromising ON-OFF current ratio, which is un-achievable in conventional CMOS devices . However, it has been found extremely challenging to recover the expected TFET performance on bulk material platform, which results from 1) inefficient gate control leading to large tunnel barrier width and low ON-current; 2) large band gap leading to high tunnel barrier and low ON-current; 3) interface trap induced leakage current leading to large SS. Utilizing the emerging 2D materials for TFET application can potentially overcome these issues, because 2D materials have 1) sizable band gap and band alignment that allow staggered- or even broken-gap type heterojunction design and lowering of tunnel barrier height, 2) ultra-thin body that provides excellent gate control and hence lowers tunnel barrier width and 3) pristine surface that greatly suppresses the trap generation. Therefore, the goal of this project is to explore (both theoretically and via experiments) 2D materials based TFETs. More specifically, we propose to employ a 2D heterostructure material platform to design and fabricate the proposed TFET device, which is radically different from all previous efforts reported in literature. This project is expected to have wide implications for the semiconductor and IT industries. Broader impact of the proposed research is also well recognized, particularly in the light of 3D integration technology now being employed worldwide, where eventual integration of ultra-low leakage and relatively temperature insensitive TFETs could be exploited to build next-generation high-performance and ultra-low power integrated circuits to support Big Data applications such as Internet of Things, social media, etc. The overall program also ties research to education at all levels.