SHF:Small: A CAD Framework for Coupled Electrical-Thermal Modeling of Interconnects in 3D Integrated Circuits

半导体行业正处于一个有趣的十字路口，传统的CMOS器件的缩放开始面临重大挑战，这些挑战有可能使40多年历史的摩尔？年代法律。3D集成电路（3D ic）提供了一种令人兴奋的替代方案，通过在单片半导体层中相互堆叠，可以无限期地持续增加功能，性能和集成密度，而不是缩放。的方式。3D集成电路由两个或多个有源（半导体）层组成，这些有源层通过钻穿称为？通过硅孔（TSV）？当使用tsv（10-100微米长）来取代最长的（几毫米）片上水平导线以及一些芯片到芯片的连接（在印刷电路板上）时，可以显著降低导线延迟和芯片功耗。此外，3D集成电路还提供了最有前途的平台来实现More-than-Moore？技术，将异质材料（硅，III-V半导体，石墨烯等）和技术（存储，逻辑，射频，混合信号，MEMS，光电等）集成在单个芯片上。然而，三维集成电路中互连的建模和分析提出了新的和更复杂的问题。与传统互连相比，嵌入在半导体材料中具有非均匀三维电流的高纵横比tsv的建模，以及互连与多个导电衬底在高频下的电磁耦合，对设计和设计自动化方法构成了新的挑战。此外，由于多个有源层及其有限的散热选择，3D集成电路中的高功率密度会产生较大的三维热梯度，因此考虑互连和周围介质的热学和电磁特性之间的耦合非常重要。最后，对精度的需求伴随着在系统级处理大量耦合互连的计算挑战，因为3D集成进一步加剧了互连问题的规模。该项目将为3D集成电路中互连和无源的耦合电-热建模和分析提供必要的基础，考虑到在超高频下与多个衬底的通用3D互连的电磁耦合以及高纵横比tsv的物理属性（包括几何形状、材料和密度），使用热感知和固有高效的技术来实现大型互连系统的全芯片建模。除了关注纳米科学和工程领域代表性不足的群体的招募和保留之外，整个项目还将研究与各级教育联系起来。

The semiconductor industry is at an interesting crossroads, where traditional scaling of CMOS devices is beginning to confront significant challenges that are threatening to derail the more than four-decades old Moore?s law. 3D integrated circuits (3D ICs) offer an exciting alternative, where in lieu of scaling, continuous increase in functionality, performance and integration density can be sustained indefinitely by stacking semiconductor layers on top of each other in a ?monolithic? manner. A 3D IC is comprised of two or more active (semiconducting) layers that have been thinned, bonded and interconnected using special vertical wires drilled through the active layers known as ?Through Silicon Vias (TSV)?. When TSVs (10-100 micrometer long) are used to replace the longest (several millimeters) on-chip horizontal wires as well as some chip-to-chip connections (on printed circuit boards), significant reduction in wire delay and chip power dissipation can be achieved. Moreover, 3D ICs also offer the most promising platform to implement ?More-than-Moore? technologies, bringing heterogeneous materials (Silicon, III-V semiconductors, Graphene, etc) and technologies (memory, logic, RF, mixed-signal, MEMS, optoelectronics, etc) on a single chip. However, modeling and analysis of interconnects in 3D ICs present new and significantly more complex problems. In contrast with traditional interconnects, the modeling of high aspect-ratio TSVs embedded in a semiconducting material with non-uniform currents in the third dimension, and electromagnetic coupling of interconnects with multiple conductive substrates at high-frequencies, constitute new challenges for design and design-automation methods. Furthermore, the high power-density in 3D ICs due to multiple active layers and their limited heat removal options give rise to large three-dimensional thermal gradients, making it important to consider the coupling between thermal and electromagnetic properties of interconnects and the surrounding media. Finally, the need for accuracy is accompanied by the computational challenge of handling a large number of coupled interconnects at the system level, as 3D integration further exacerbates the size of the interconnect problem.This project will develop the necessary foundations for coupled electrical-thermal modeling and analysis of interconnects and passives in 3D ICs, considering the electromagnetic coupling of general 3D interconnects with multiple substrates at ultra-high frequencies as well as the physical attributes of high aspect-ratio TSVs (including geometry, material and density), using thermally-aware and inherently efficient techniques to enable full-chip modeling of the large system of interconnects. The overall program also ties research to education at all levels besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.