SHF:Small: A CAD Framework for Coupled Electrical-Thermal Modeling of Interconnects in 3D Integrated Circuits

SHF:Small：3D 集成电路互连电热耦合建模的 CAD 框架

• 批准号: 0917385
• 负责人: Kaustav Banerjee
• 金额: $ 45万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-08-01 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0917385&HistoricalAwards=false
• 关键词: SHF; Small; CAD; Framework; Coupled

The semiconductor industry is at an interesting crossroads, where traditional scaling of CMOS devices is beginning to confront significant challenges that are threatening to derail the more than four-decades old Moore?s law. 3D integrated circuits (3D ICs) offer an exciting alternative, where in lieu of scaling, continuous increase in functionality, performance and integration density can be sustained indefinitely by stacking semiconductor layers on top of each other in a ?monolithic? manner. A 3D IC is comprised of two or more active (semiconducting) layers that have been thinned, bonded and interconnected using special vertical wires drilled through the active layers known as ?Through Silicon Vias (TSV)?. When TSVs (10-100 micrometer long) are used to replace the longest (several millimeters) on-chip horizontal wires as well as some chip-to-chip connections (on printed circuit boards), significant reduction in wire delay and chip power dissipation can be achieved. Moreover, 3D ICs also offer the most promising platform to implement ?More-than-Moore? technologies, bringing heterogeneous materials (Silicon, III-V semiconductors, Graphene, etc) and technologies (memory, logic, RF, mixed-signal, MEMS, optoelectronics, etc) on a single chip. However, modeling and analysis of interconnects in 3D ICs present new and significantly more complex problems. In contrast with traditional interconnects, the modeling of high aspect-ratio TSVs embedded in a semiconducting material with non-uniform currents in the third dimension, and electromagnetic coupling of interconnects with multiple conductive substrates at high-frequencies, constitute new challenges for design and design-automation methods. Furthermore, the high power-density in 3D ICs due to multiple active layers and their limited heat removal options give rise to large three-dimensional thermal gradients, making it important to consider the coupling between thermal and electromagnetic properties of interconnects and the surrounding media. Finally, the need for accuracy is accompanied by the computational challenge of handling a large number of coupled interconnects at the system level, as 3D integration further exacerbates the size of the interconnect problem.This project will develop the necessary foundations for coupled electrical-thermal modeling and analysis of interconnects and passives in 3D ICs, considering the electromagnetic coupling of general 3D interconnects with multiple substrates at ultra-high frequencies as well as the physical attributes of high aspect-ratio TSVs (including geometry, material and density), using thermally-aware and inherently efficient techniques to enable full-chip modeling of the large system of interconnects. The overall program also ties research to education at all levels besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.

半导体行业正处于一个有趣的十字路口，CMOS器件的传统缩放开始面临重大挑战，这些挑战有可能使40多年前的摩尔？s定律。3D集成电路（3D IC）提供了一个令人兴奋的替代方案，其中代替缩放，功能，性能和集成密度的持续增加可以通过在彼此顶部堆叠半导体层来无限期地维持？铁板一块方式 一个三维集成电路是由两个或两个以上的有源（半导体）层已减薄，结合和互连使用特殊的垂直线钻通过有源层称为？硅通孔（TSV）？。 当TSV（10-100微米长）被用于替换最长（几毫米）的芯片上水平导线以及一些芯片到芯片连接（在印刷电路板上）时，可以实现导线延迟和芯片功耗的显著降低。此外，3D IC还提供了最有前途的实施平台？比摩尔还厉害在一个芯片上集成了多种技术，将异质材料（硅、III-V半导体、石墨烯等）和技术（存储器、逻辑、RF、混合信号、MEMS、光电子等）整合在一起。 然而，3D IC中互连的建模和分析提出了新的和明显更复杂的问题。与传统的互连相比，嵌入在半导体材料中的高深宽比TSV在第三维中具有非均匀电流的建模，以及互连与多个导电衬底在高频下的电磁耦合，对设计和设计自动化方法构成了新的挑战。 此外，由于多个有源层及其有限的散热选项，3D IC中的高功率密度引起大的三维热梯度，因此考虑互连和周围介质的热和电磁特性之间的耦合非常重要。最后，由于3D集成进一步加剧了互连问题的规模，因此对精度的需求伴随着在系统级处理大量耦合互连的计算挑战。本项目将为3D IC中互连和无源器件的耦合电热建模和分析奠定必要的基础，考虑到一般3D互连与多个衬底在超高频率下的电磁耦合以及高深宽比TSV的物理属性（包括几何形状、材料和密度），使用热感知和固有的高效技术来实现大型互连系统的全芯片建模。整个计划还将研究与各级教育联系起来，除了专注于招募和保留纳米科学和工程领域代表性不足的群体。