CPA-DA-T: A Collaborative Framework for Design and Fabrication of Metallic Carbon Nanotube based Interconnect Structures for VLSI Circuits and Systems Applications

CPA-DA-T：用于设计和制造用于超大规模集成电路和系统应用的基于金属碳纳米管的互连结构的协作框架

• 批准号: 0811880
• 负责人: Kaustav Banerjee
• 金额: $ 100万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2013-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811880&HistoricalAwards=false
• 关键词: CPA; DA; Collaborative; Framework; Design

Proposal ID: 0811880PI Name: Kaustav BanerjeeInstitution: University of California-Santa BarbaraTitle: A Collaborative Framework for Design and Fabrication of Metallic Carbon Nanotube based Interconnect Structures for VLSI Circuits and Systems Applications ABSTRACTThe semiconductor industry is confronting an acute problem in the interconnect area due to the limited current carrying capability of copper wires, which are presently used to connect billions of transistors in every integrated circuit (IC) including microprocessors that are vital for information transmission, processing and storage. As IC feature sizes continue to be scaled below 45 nanometer, copper wires exhibit significant ?size effects? resulting in a sharp rise in their resistivity, which, in turn, has adverse impact both on their performance as well as reliability---in the form of current carrying capacity. This limitation of copper interconnects has been recently highlighted by various leading semiconductor companies around the world as well as in the International Technology Roadmap for Semiconductors (ITRS), and threatens to slow down or even stall the traditional growth of the semiconductor and related industries. Hence, it is critical to identify and develop new interconnect solutions. Carbon nanotubes, tiny nanostructures 80,000 times narrower than a human hair, are known to have amazing electrical, thermal and mechanical properties, and can potentially address the challenges faced by copper and thereby extend the lifetime of ?electrical interconnects?. Most of these outstanding properties arise from the ?low-dimensionality? of CNTs---since they are essentially 1-dimensional structures. The investigators seek to, for the first time, understand how these tiny structures can be efficiently integrated into microprocessors and other circuitry to address the dire need for faster and more reliable on-chip wiring. The CNT interconnect structures also offer exciting prospects for design of ultra high-density energy storage elements (such as capacitors and inductors), as well as various system-level architectural innovations. This collaborative four-year project brings together a team of scientists and engineers for addressing the key scientific and engineering challenges associated with the design and fabrication of CNT interconnect structures for various circuits and systems applications. The investigators employ an interdisciplinary approach that combines innovative process technology and circuit/system architecture development supported by rigorous modeling, analysis, and metrology techniques. This presents an outstanding opportunity to truly demonstrate the prospects of CNTs in overcoming one of the major limitations of nanometer scale ICs, and is expected to have wide implications for the semiconductor industry. This research will help scaling of CMOS circuits to its ultimate limits and also open new opportunities in mixed-signal, analog and radio-frequency (RF) signal processing applications as well as in 3-dimensional integrated circuit design, thereby maintaining U.S. competitiveness in the worldwide semiconductor market. Broader impact of the research includes emerging off-chip applications of carbon nanotubes as ?solder bumps? and also as an excellent thermal interface material for heat removal from chips and printed circuit boards. The overall program also ties research to education at all levels (K-12, undergraduate, graduate, continuing-education) partly via participation in programs designed by education professionals, besides focusing on recruitment and retention of underrepresented groups in nanoscience and engineering.

提案ID：0811880 PI姓名：Kaustav Banerjee机构：加州大学圣巴巴拉分校标题：用于VLSI电路和系统应用的基于金属碳纳米管的互连结构的设计和制造的协作框架 由于铜线的有限载流能力，半导体工业在互连领域面临着一个严重的问题，铜线目前用于连接每个集成电路（IC）中的数十亿个晶体管，包括对信息传输、处理和存储至关重要的微处理器。 随着IC特征尺寸继续缩小到45纳米以下，铜线表现出显着？规模效应？导致其电阻率急剧上升，这反过来又对它们的性能以及可靠性（以载流能力的形式）产生不利影响。铜互连的这种局限性最近已被世界各地的各种领先半导体公司以及国际半导体技术路线图（ITRS）所强调，并有可能减缓甚至停止半导体和相关行业的传统增长。 因此，识别和开发新的互连解决方案至关重要。碳纳米管是一种比人类头发窄80，000倍的微小纳米结构，已知具有惊人的电，热和机械性能，并且可以潜在地解决铜所面临的挑战，从而延长铜的寿命。电气互连？这些优秀的财产大多来自？低维度碳纳米管-因为它们基本上是一维结构。 研究人员首次试图了解这些微小结构如何有效地集成到微处理器和其他电路中，以满足对更快、更可靠的片上布线的迫切需求。CNT互连结构还为超高密度储能元件（如电容器和电感器）的设计以及各种系统级架构创新提供了令人兴奋的前景。 这个为期四年的合作项目汇集了一个科学家和工程师团队，以解决与各种电路和系统应用的CNT互连结构的设计和制造相关的关键科学和工程挑战。研究人员采用跨学科的方法，结合了创新的工艺技术和电路/系统架构开发，并得到严格的建模，分析和计量技术的支持。这为真正展示CNT在克服纳米级IC的主要限制之一方面的前景提供了一个绝佳的机会，预计将对半导体行业产生广泛的影响。 这项研究将有助于将CMOS电路扩展到其极限，并在混合信号，模拟和射频（RF）信号处理应用以及三维集成电路设计中开辟新的机会，从而保持美国在全球半导体市场的竞争力。 更广泛的影响，研究包括新兴的芯片外应用的碳纳米管？焊料凸点？并且还作为用于从芯片和印刷电路板散热的优异的热界面材料。整个计划还将研究与各级教育（K-12，本科，研究生，继续教育）联系起来，部分通过参与教育专业人士设计的计划，除了专注于招聘和保留纳米科学和工程中代表性不足的群体。