SGER: Design Technologies for Nanoscale VLSI

摘要0739623 Marios C. Papaefthymiou的密歇根大学智力MeritThe持续缩放的半导体工艺技术带来了新的挑战，在设计的超大规模集成电路系统，而在同一时间激励新的方法来解决这些问题。高端集成系统的功率密度已经达到了性能限制水平。器件可变性的增加会导致更大的延迟不确定性，从而要求使用更大的设计裕度并进一步限制性能。 然而，每个器件的硅继续以指数速度下降，使硅面积的新用途成为可能。 本研究计画将探讨下一代奈米级超大型积体电路系统之设计技术。具体而言，该项目将专注于探索所谓的电荷恢复设计技术，这些技术能够在新的功率效率水平上运行，同时减少由于器件可变性而导致的不确定性。在传统的VLSI设计中，电容器在电源和地之间突然切换，经历高峰电流，并将其所有存储的能量作为热耗散在电阻器件上。此外，设备的可变性导致显着的不确定性，在传统的分布网络的时钟到达时间与缓冲区。与传统的集成系统相比，电荷恢复设计逐渐切换电容器，保持低峰值电流，并将任何未耗散的能量返回到电源。因此，电荷恢复设计可以潜在地导致开关功率和栅极泄漏的大幅降低。此外，由于它们依赖于无缓冲器的谐振时钟分配网络，电荷恢复设计也有望大幅降低时钟延迟不确定性。 迄今为止，电荷回收的巨大潜力仍未得到开发，因为它偏离了既定的设计做法。该项目的主要目标是探索和评估电荷恢复技术的潜力，包括电路，设计方法和计算架构，以实现具有前所未有的功率效率和性能水平的纳米级硅基超大规模集成电路系统。更广泛的影响拟议的研究预计将有一个实现下一代超大规模集成电路系统的重大影响，促进发现，教学和学习新的设计技术，解决关键问题innanoscale过程节点。更广泛的成果，拟议的努力包括研究活动的整合到研究生水平的课程，讲座和项目的发展，为先进的本科课程，以及直接参与电气工程和计算机科学专业通过高级设计项目。根据PI在促进广泛参与方面的良好记录，拟议的研究和教育活动将包括代表性不足的群体的参与者。

ABSTRACT0739623Marios C. PapaefthymiouUniversity of MichiganIntellectual MeritThe continuing scaling of semiconductor process technology brings about new challenges in the designof VLSI systems, while at the same time motivating new approaches for addressing them. Power density inhigh-end integrated systems has already reached performance-limiting levels. Increased device variabilityresults in greater delay uncertainty, dictating the use of larger design margins and further limiting performance. Yet, silicon per device continues to decrease at exponential rates, enabling novel uses of siliconarea. This research project will investigate next-generation design technologies for the realization of nanoscale VLSI systems in silicon. Specifically, this project will focus on the exploration of so-called charge recovery design technologies that enable operation at new levels of power-efficiency while reducing uncertainty due to device variability. In conventional VLSI design, capacitors are switched abruptly between supply and ground, experiencing high peak currents and dissipating all their stored energy as heat across resistive devices. Furthermore, device variability leads to significant uncertainty in the clock arrival times of conventional distribution networks with buffers. In contrast to conventional integrated systems, charge-recovery designs switch capacitors gradually, maintaining low peak currents and returning any undissipated energy back to the power supply. Therefore, charge-recovery designs can potentially lead to substantial reductions in switching power and gate leakage. Moreover, since they rely on buffer-less resonant clock distribution networks, charge-recovery designs are also expected to yield substantial reductions in clock delay uncertainty. The significant potential of charge recovery has so far remained untapped, as it represents a departure from established design practices. The main objective of this project is to explore and assess the potential of charge-recovery technologies, including circuitry, design methodologies, and computing architectures for realizing nanoscale silicon-based VLSI systems with unprecedented levels of power efficiency and performance. Broader ImpactsThe proposed research is expected to have a significant impact on the realization of next-generation VLSIsystems, promoting discovery, teaching, and learning in novel design technologies that address key issues innanoscale process nodes. Broader outcomes of the proposed effort include the integration of research activitiesinto graduate-level courses, the development of lectures and projects for advanced undergraduate-levelcourses, as well as the direct involvement of electrical engineering and computer science majors throughsenior-level design projects. Consistent with the PI's proven record in promoting broad participation, theproposed research and education activities will include participants from underrepresented groups.A1