Synchronous VLSI Circuit Optimization via Integrated Retiming and Clock Skew Scheduling

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This project is cooperative between the University of Michigan (Papaefthymiou) and the University of Rochester (Friedman). It is exploring electronic design automation methods for optimizing high performance, high complexity VLSI/ULSI circuits. The focus is on retiming and clock scheduling, two complementary circuit optimization strategies that have attracted significant attention. Retiming is an architectural-level transformation method that speeds up a synchronous digital design. Clock scheduling is a circuit-level optimization that increases the operating speed of a digital design. The approach is to merge these two methods into a single powerful optimization process that will handle comprehensive delay models. Problems being investigated are: (1) Finding enhanced circuit models that consider physical and electrical issues related to submicrometer technologies; (2)Developing a theoretical yet practical framework for simultaneous retiming and clock scheduling based on these physical & electrical models; (3) Designing and evaluating polynomial-time approximation algorithms for integrated retiming and clock scheduling. Software developed during the project is being widely distributed.