Synchronous VLSI Circuit Optimization via Integrated Retiming and Clock Skew Scheduling

通过集成重定时和时钟偏差调度实现同步 VLSI 电路优化

• 批准号: 9610108
• 负责人: Marios Papaefthymiou
• 金额: $ 37万
• 依托单位: Regents of the University of Michigan - Ann Arbor
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-06-01 至 2001-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9610108&HistoricalAwards=false
• 关键词: Synchronous; VLSI; Circuit; Optimization; via

This project is cooperative between the University of Michigan (Papaefthymiou) and the University of Rochester (Friedman). It is exploring electronic design automation methods for optimizing high performance, high complexity VLSI/ULSI circuits. The focus is on retiming and clock scheduling, two complementary circuit optimization strategies that have attracted significant attention. Retiming is an architectural-level transformation method that speeds up a synchronous digital design. Clock scheduling is a circuit-level optimization that increases the operating speed of a digital design. The approach is to merge these two methods into a single powerful optimization process that will handle comprehensive delay models. Problems being investigated are: (1) Finding enhanced circuit models that consider physical and electrical issues related to submicrometer technologies; (2)Developing a theoretical yet practical framework for simultaneous retiming and clock scheduling based on these physical & electrical models; (3) Designing and evaluating polynomial-time approximation algorithms for integrated retiming and clock scheduling. Software developed during the project is being widely distributed.

该项目是密歇根大学（Papaefthymiou）和罗切斯特大学（Friedman）合作开展的。它正在探索优化高性能、高复杂度VLSI/ULSI电路的电子设计自动化方法。重点是重定时和时钟调度，两个互补的电路优化策略，吸引了显着的关注。 重定时是一种架构级转换方法，可加快同步数字设计的速度。时钟调度是一种电路级优化，可提高数字设计的运行速度。该方法是将这两种方法合并为一个强大的优化过程，将处理全面的延迟模型。正在调查的问题是：（1）寻找考虑与亚微米技术相关的物理和电气问题的增强电路模型;（2）基于这些物理电气模型开发同时重定时和时钟调度的理论和实践框架&;（3）设计和评估用于集成重定时和时钟调度的多项式时间近似算法。项目期间开发的软件正在广泛分发。