GOALI (Industry-University Collaborative Project): Collaborative Research: Scalable Techniques for Detecting Small-Delay Defects in Nanometer Integrated Circuits
GOALI (Industry-University Collaborative Project): Collaborative Research: Scalable Techniques for Detecting Small-Delay Defects in Nanometer Integrated Circuits
批准号:
0823835
负责人:
Krishnendu Chakrabarty
金额:
$23.52万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2008
资助国家:
美国
项目状态:
已结题
起止时间:
2008-09-01 至 2011-08-31
中文摘要
本项目的目标是针对纳米集成电路中的小延迟缺陷开发新的测试技术。该方法基于使用输出偏差度量作为小延迟缺陷的替代“长路径”覆盖度量。该项目将与AMD公司和其他行业合作伙伴合作进行。智能优点:由工艺变化、串扰、电源噪声和阻性开路/短路等引起的小延迟缺陷是半导体行业的主要质量和可靠性问题。目前的行业做法不仅不足以处理小延迟缺陷,而且测试成本也在飙升(估计超过制造成本的50%)。该项目专注于使用可扩展的方法生成测试,这些方法可以为工业电路提供全面的缺陷筛选。它包括以下组件:(I)对延迟故障进行建模的门延迟缺陷概率度量;(Ii)使用门延迟缺陷概率来计算输出偏差;(Iii)布局感知、基于偏差的测试模式选择/生成,以实现高缺陷覆盖率。广泛影响:该项目将导致更高的出厂产品质量、更高的现场可靠性和更低的测试成本。对社会的好处包括用于医疗保健的可靠电子产品,用于服务器、天气预报、金融交易等的更便宜和可靠的计算平台,以及实现备受欢迎的汽车应用的零缺陷。学生将通过研究经验、课程学习和相关的行业实习来为劳动力进行培训。将作出协调一致的努力,让代表性不足的团体参与进来,例如通过半导体研究公司奖学金计划。将在主要会议上介绍教程并组织特别会议。
英文摘要
ObjectiveThe objective of this project is to develop new test techniques that target small-delay defects in nanoscale integrated circuits. The approach is based on the use of the output-deviations measure as a surrogate "long-path" coverage metric for small-delay defects. The project will be carried out in partnership with AMD Corporation and other industrial collaborators. Intellectual Merit: Small-delay defects, induced by process variations, crosstalk, power-supply noise, and resistive opens/shorts, etc., are major quality and reliability concerns in the semiconductor industry. Current industry practices are not only inadequate for small-delay defects, but test costs are skyrocketing as well (estimated to be more than 50% of manufacturing cost). This project is focused on test generation using scalable methods that can provide comprehensive defect screening for industrial circuits. It includes the following components: (i) a gate-delay-defect probability measure to model delay faults; (ii) use of gate-delay-defect probabilities for computing output deviations; (iii) layout-aware, deviation-based test-pattern selection/generation for high defect coverage.Broader Impacts: This project will lead to higher shipped-product quality, increased in-field reliability, and reduced test cost. Benefits for society include reliable electronics for healthcare, cheaper and dependable computing platforms for servers, weather forecasting, financial transactions, and more, and realization of the much sought-after zero-defects for automotive applications. Students will be trained for the workforce through research experience, coursework, and relevant industry internships. A concerted effort will be made to involve under-represented groups, for example through the Semiconductor Research Corporation fellowship programs. Tutorials will be presented and special sessions will be organized at major conferences.
期刊论文(0)
专著(0)
科研奖励(0)
会议论文
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财政年份:2018
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依托单位:
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依托单位:
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依托单位:
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依托单位:
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财政年份:2010
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依托单位:
U.S.-India Planning Visit: Collaborative Research on Algorithms for Digital Microfluidic Biochips
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资助金额:$0.44万
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依托单位:
Optimization of Test and Diagnosis Infrastructure for Multicore Chips
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依托单位:
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批准号:0914895
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U.S.-Japan Cooperative Science: Efficient Test and Diagnosis Techniques for System-on-Chip
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负责人:Krishnendu Chakrabarty
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依托单位:
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依托单位: