CIF: Small: Digital Mitigation of Spurious Tones in Fractional-N PLLs

分数N锁相环(PLL)是包括蜂窝电话和无线局域网在内的大多数现代无线通信系统中的关键部件。遗憾的是，传统PLL引入的误差包含被称为杂音的周期干扰，对于典型的无线应用，只有使用增加功耗和成本的技术才能充分抑制该干扰。此外，随着集成电路(IC)技术继续向更小的尺寸扩展，这些技术变得不那么有效。因此，杂音问题对无线通信系统的功耗、成本和可制造性产生了负面影响，并且随着集成电路工艺的发展符合摩尔-S定律，这个问题变得越来越严重。当调制器S量化噪声受到锁相环中非理想电路行为的非线性影响时，会产生伪音。这项研究的目标是开发一种称为连续再计量器的调制器替代品，以避免这一问题。连续再量化器的工作原理不同于？调制器，其量化噪声对非线性引起的杂音的影响要小得多。研究任务是1)进一步发展支持连续请求器的理论以提高其性能，2)研究如何在电路级优化锁相环，以利用连续请求器提供的对非线性失真的降低的敏感性，以及3)开发概念验证小数N锁相环IC，其符合诸如IEEE 802.16等苛刻的无线标准，并且在最小化功耗和电路面积方面超过当前技术水平。

CIF: Small: Digital Mitigation of Spurious Tones in Fractional-N PLLsFractional-N phase locked loops (PLLs) are critical components in most modern wireless communication systems including cellular telephones and wireless local area networks. Unfortunately, the error introduced by conventional PLLs contains period disturbances referred to as spurious tones, which only can be suppressed sufficiently for typical wireless applications with techniques that increase power consumption and cost. Furthermore, these techniques become less effective as integrated circuit (IC) technology continues to scale to smaller dimensions. Therefore, the spurious tone problem negatively affects power consumption, cost, and manufacturability of wireless communication systems, and the problem gets worse as IC technology scales with Moore?s Law.The ÄÓ modulator in a conventional PLL is the fundamental cause of spurious tones. The spurious tones are induced when the ÄÓ modulator?s quantization noise is subjected to nonlinearity from non-ideal circuit behavior in the PLL. The goal of this research is to develop a ÄÓ modulator replacement, called a successive requantizer, that avoids this problem. The successive requantizer has a different principle of operation than a ÄÓ modulator and its quantization noise is much less susceptible to nonlinearity-induced spurious tones. The research tasks are 1) to further develop the theory underlying successive requantizers to improve their performance, 2) to investigate how PLLs can be optimized at the circuit level to take advantage of the reduced sensitivity to nonlinear distortion offered by successive requantizers, and 3) to develop a proof-of-concept fractional-N PLL IC enabled by the theoretical results of the project that is compliant with a demanding wireless standard such as IEEE 802.16 and exceeds the present state of the art in terms of minimizing power consumption and circuit area.