SHF:Small: Locality-Driven Architectures for Scalable Multicore Systems

半导体制造业在过去35年里的连续创新，使摩尔定律将过去房间大小的计算机系统变成了由数十亿个晶体管组成的单个芯片。这些集成度迫使计算机系统设计朝着并行化方向发展，包括单芯片多处理器和片上系统。今天，这些芯片有几十个单独的处理器，但未来的扩展将使数百或数千个处理器在一个芯片上成为可能。 出现了两个重要的挑战，可能会阻碍多核系统的性能扩展。 首先，虽然在可预见的未来，技术扩展将继续增加晶体管数量，但功率和热限制将阻止所有晶体管同时全速运行，只有一小部分晶体管可以全速运行。第二，从多核芯片到其外部存储器和其他处理器的通信路径的速度正在以缓慢的速率增加。由于这些通信路径必须由越来越多的片上处理核心共享，因此必须尽可能有效地使用这些路径，以防止它们成为系统的瓶颈。本项目旨在开发新的计算机硬件和软件机制，在高性能系统中利用数据局部性，包括重复使用数据项以及使用存储器中彼此相邻的多个数据项。特别是，该项目将开发用于批量数据传输的硬件机制，支持重命名，打包和集成到虚拟内存系统中。PI还将在片上存储器系统中开发硬件机制，使其能够适应不同的编程原语以及处理核心之间的不同一致性需求。 该机制将在有效性和可编程性方面使用一系列的应用程序进行评估。这项研究旨在开发对新兴的并行多核芯片至关重要的技术，如果没有这些技术，这些芯片将无法满足性能和功耗目标。以高能效的方式实现增强的性能对于未来计算平台的所有部署至关重要，包括用于科学、商业和国家安全的平台。这项研究的更广泛的影响将包括培训研究生和本科生作为研究人员，同时也致力于提高代表性不足的群体在计算中的参与。主要的推广活动将包括参加夏令营，吸引高中女生学习计算机科学。

The successive innovations in semiconductor manufacturing over the last 35 years of Moore's law have turned what used to be a room-sized computer system into a single chip composed of billions of transistors. These levels of integration have forced a change toward parallelism in computer system design, including both single-chip multiprocessors and systems-on-a-chip. Today, these chips have a few tens of individual processors but future scaling will make possible hundreds or thousands of them on a chip. Two important challenges have emerged which threaten to hinder performance scaling in multicore systems. First, while technology scaling will continue to enable increased transistor counts for the foreseeable future, power and thermal limitations will prevent all but a small fraction of them to be operating simultaneously at full speed. Second, the speed of the communication paths from the multicore chip to its external memory and to other processors is increasing at a slow rate. Because these communication paths must be shared by more and more on-chip processing cores, the paths must be used as efficiently as possible to prevent them from becoming a bottleneck in the system.This project seeks to develop new computer hardware and software mechanisms that exploit data locality in high performance systems, including repeated use of a data item as well as use of multiple data items that lie near one another in memory. In particular, the project will develop hardware mechanisms for bulk data transfers that support renaming, packing, and integration into the virtual memory system. The PI will also develop hardware mechanisms in the on-chip memory system that will allow it to adapt to different programming primitives as well as to different coherence needs among the processing cores. The mechanisms will be evaluated in terms of effectiveness and programmability using a range of applications.This research aims to develop technologies critical to emerging parallel multicore chips, without which such chips will not be able to meet performance and power goals. Enabling enhanced performance in a power-efficient manner is critical to all deployments of future computing platforms, including those for science, commerce, and national security. The broader impact of this research will include training graduate and undergraduate students as researchers, while also working to increase participation of underrepresented groups in computing. The primary outreach activity will include participation in a summer camp to attract high-school girls to computer science.