SHF: Small: 3D Integration of Sub-Threshold Multi-core Co-processor for Ultra Lower Power Computing

“这项奖励是根据2009年美国复苏和再投资法案（公法111-5）资助的。”最近越来越流行的一种完全不同的电路设计方法是亚阈值电路，当速度不是主要限制时，电源被设置在晶体管阈值电压以下以获得节能。在亚阈值区域设计的单个电路或处理元件运行速度较慢，但可以通过并行运行许多电路来提高电路的吞吐量。因此，具有许多亚阈值核的处理结构可以成为面向吞吐量的并行应用程序的合适平台。本提案探讨了用于低功耗计算的亚阈值和超阈值电路的3D模堆的可行性。更具体地说，我们的亚阈值模具包含许多小的亚阈值核心，而我们的超阈值模具由几个大的超阈值核心组成。子阈值内核用作协处理器，以超低功耗执行大规模并行、高吞吐量、低/中等性能任务，而主超阈值处理器处理高性能串行任务。这种新的协作计算硬件有望为许多有用的嵌入式软件应用程序提供一个可行的平台，这些应用程序既需要高性能/功耗任务，也需要低性能/功耗任务。3D集成将允许每个模具利用针对亚阈值和超阈值操作优化的工艺技术，并无缝集成到单个系统中。基于TSV（通过硅通孔）的3D通信不需要片外接入，从而进一步降低了功耗。亚阈值电路目前用于一些低功耗应用，如手表，助听器，分布式传感器网络，滤波器，甚至流水线微处理器。3D集成技术已经应用于嵌入式领域，高性能处理器行业正在积极评估该技术在通用计算中的应用。这项研究将填补使3d集成亚阈值多核协处理器成为现实所需的关键空白。

"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."A fundamentally different approach for circuit design that has recently gaining popularity is sub-threshold circuits, where the power supply is set below the transistor threshold voltage to obtain energy savings when speed is not the primary constraint. Individual circuits or processing element designed at sub-threshold region operates slowly, but throughput of the circuit can be improved by operating many of them in parallel. Hence, a processing fabric with many sub-threshold cores can be a suitable platform for throughput-oriented parallel applications. This proposal explores the viability of 3D die-stacking of sub-threshold and super-threshold circuits for low power computing. More specifically, our sub-threshold die contains many small sub-threshold cores, whereas our super-threshold die consists of several large super-threshold cores. The sub-threshold cores are used as co-processors to execute massively parallel, high-throughput, low/mid-performance tasks at ultra low power, while the main super-threshold processors handle high-performance sequential tasks. This new cooperative computing hardware is expected to provide a viable platform for many useful embedded software applications that require both high-performance/power tasks as well as low-performance/power tasks. 3D integration will allow each die to utilize the process technology optimized for sub- and super-threshold operation and be seamlessly integrated into a single system. TSV (through silicon via) based 3D communication requires no off-chip access, thereby reducing power consumption further. Sub-threshold circuits are currently used for some low-power applications such as watches, hearing aids, distributed sensor networks, filters, and even pipelined micro-processors. 3D integration is already available in the embedded domain, and the high-performance processor industry is actively evaluating this technology for general purpose computing. This research will fill a critical gap that is needed to make 3D-integrated sub-threshold multi-core co-processors a reality.