SHF: Small: Collaborative Research: Architecting Technology Enabled Phase Change Memory Systems

几十年来，动态随机存取存储器(DRAM)一直被用作计算机系统中的主存储器。然而，DRAM技术同时面临可伸缩性和电源问题。相变存储器(PCM)以其优异的可扩展性，成为实现高容量、超高密度主存系统的一种极具吸引力的DRAM替代方案。纳米材料工程的最新进展也使得使用纳米结构(如纳米线)制造相变存储器成为可能，与传统的薄膜基片相比，这种结构显示出超低的编程功率。尽管技术规模和先进的材料工程提供了更小、更密集的器件，但它们使得设计可靠、节能和高性能的相变存储系统越来越具有挑战性。如果不加注意，这些挑战将很快成为未来相变存储系统的阻碍因素，因为它们要么阻止它们缩小到更小的特征尺寸，要么导致这些系统的低效运行。该合作研究项目旨在随着底层处理技术的不断扩展而提高相变存储系统的效率，包括：(1)相变存储的跨层工艺变化表征、建模和缓解(2)基于纳米线的PCM设计探索和(3)抗漂移弹性相变存储系统。此外，该项目将开发一个全面的全系统模拟基础设施，包括PCM器件/阵列/体系结构多尺度模型和体系结构/操作系统技术，使计算机体系结构设计界能够根据先进的工艺技术和材料工程研究采用新兴相变存储系统的权衡和优化。这一合作研究项目将促进基于超高密度、低功耗和可靠相变的非易失性存储系统，以最有效地利用新兴的纳米级材料和制造技术，以应对当今计算机设计界面临的巨大“存储墙”挑战。随着CPU核心数量的增加和工作负载变得更加内存密集型，它可以极大地帮助高性能计算保持其历史性的扩展，从而使从高端服务器到低端嵌入式系统的众多现实应用程序受益。这一合作研究项目还将通过让代表性不足的群体参与、为教育和培训传播研究基础设施以及接触非易失性存储器设计行业来为社会做出贡献。

Dynamic random access memory (DRAM) has been used as the main memory in computer systems for decades. However, DRAM technologies are facing both scalability and power issues. With the superior scalability, phase-change memory (PCM) has become an attractive DRAM alternative to implement high-capacity, ultra-dense main memory systems. Recent advances in nano-scale material engineering have also enabled fabricating phase change memory using nano-scale structures (e.g. nano-wire), which exhibit ultra-low programming power than the conventional thin-film based substrates. Although technology scaling and advanced material engineering provide smaller and denser devices, they make architecting reliable, power-efficient and high-performance phase change memory systems increasingly challenging. If left unattended, these challenges will soon become showstoppers of future phase change memory systems by either preventing them from scaling down to smaller feature sizes or resulting in the inefficient operation of these systems. This collaborative research project aims to improve the efficiency of phase change memory systems as the underlying processing technology scaling continues, including: (1) Cross-layer process variation characterization, modeling and mitigation for phase change memory (2) Nano-wire based PCM design exploration and (3) Resistance drift resilient phase change memory system. In addition, this project will develop a comprehensive full-system simulation infrastructure that consists of PCM device/array/architecture multi-scale models and architecture/OS techniques that will allow the computer architecture design community to study the trade offs and optimizations of employing emerging phase change based memory systems in light of advanced process technology and material engineering. This collaborative research project will facilitate ultra-density, low-power and reliable phase change based non-volatile memory systems to most effectively leverage emerging nano-scale material and fabrication technologies to tackle the grand "Memory Wall" challenge faced in today's computer design community. It can greatly contribute to enabling high-performance computing to stay on track with its historic scaling as the number of CPU cores increases and workloads become more memory intensive, and hence benefit numerous real-life applications running from high-end servers to low-end embedded systems. This collaborative research project will also contribute to society through engaging under-represented groups, research infrastructure dissemination for education and training, and outreach to non-volatile memory design industries.