CCF: Small: Improving Trace Based Simulation of On-Chip Networks

智能手机等移动设备和数据中心使用的服务器中的未来计算芯片将包含许多处理器、存储器和专门的功能单元，通过复杂的片上网络连接。片上网络是影响芯片性能、功耗和成本的关键设计元素。因此，迫切需要工具和技术来快速探索片上网络的设计空间，以创建针对给定应用和/或细分市场进行优化的网络。基于轨迹的仿真被广泛应用于片上网络的设计和优化。但是，基于跟踪的模拟可能会导致有关网络行为的错误和误导性结论，因为跟踪不能准确地模拟应用程序的数据包注入速率。在这个项目中，研究人员开发了一些技术来克服基于轨迹的仿真的这一局限性，它允许快速的设计空间探索片上网络的设计空间，其精度接近于全系统仿真，但仿真时间与基于轨迹的仿真相似。通过对具有不同链路延迟的全连接网络拓扑上的应用程序的多次运行进行采样来推断包之间的依赖关系。使用依赖信息扩展的跟踪可以更准确地对应用程序的数据包注入速率进行建模。基于现场可编程门阵列的加速技术被用于收集和分析网络轨迹，并开发了一个能够处理添加了数据包依赖信息的轨迹的快速多线程网络仿真器，该工作的更广泛的影响将是通过一个经过验证的扩展了数据包依赖信息的基准轨迹库和一个多线程网络仿真器，该网络仿真器可以被研究界用来设计和优化具有数百个处理器的片上网络。

Future computing chips inside mobile devices such as smart phones, and servers used in data centers will contain many processors, memories and specialized functional units, connected by a sophisticated on-chip network. The on-chip network is a critical design element that influences the performance, power consumption, and cost of the chip. Hence, there is a compelling need for tools and techniques to explore the design space of an on-chip network quickly to create networks that are optimized for a given application and/or a market segment. Trace-based simulation is used widely to design and optimize on-chip networks. However, trace-based simulation can result in incorrect and misleading conclusions about network behavior because, a trace does not model the packet injection rate of the application accurately. In this project, the investigators develop techniques to overcome this limitation of trace-based simulation, which allows for rapid design space exploration of on-chip networks with accuracy approaching that of full-system simulation but with simulation time similar to trace-based simulation.Dependencies between packets are inferred by sampling multiple runs of an application on a fully connected network topology with different link latencies. Traces augmented with dependency information, model the packet injection rate of an application more accurately. FPGA-based acceleration is used to collect and analyze traces and a fast multithreaded network simulator that is capable of processing traces augmented with packet dependency information, is developed.The broader impact of the work will be through a validated repository of benchmark traces augmented with the packet dependency information and a multi-threaded network simulator that can be used by the research community to design and optimize on-chip networks with hundreds of processors.