SHF: Medium: Collaborative Research: 3D Integration of Heterogeneous Dies

在过去的40年里，电子设备的巨大进步很大程度上借鉴了摩尔定律。摩尔定律预测半导体芯片中的晶体管密度会稳步增加，同时成本和功率也会随之提高。但摩尔定律现在正在放缓，而成本的改善现在依赖于非常大的产量，以证明在制造基础设施上投资数十亿美元是合理的。在可选择的芯片设计方法中，三维芯片设计目前显示出显著的势头和商业产品的前景。三维芯片可以由传统二维芯片的垂直堆叠和通过硅孔连接而成。尽管有许多尚未解决的技术问题，这种三维芯片减少了形状因素和互连，同时提高了成品率。本研究探索异质三维芯片设计，寻求结合不同类型二维芯片（不同类型的存储器，快速逻辑，低功耗逻辑，fpga，模拟电路，微纳米机电元件等）的灵活性，这些芯片无法在单个传统模具上可靠地制造。本研究将通过挖掘各方面的异质性，降低3D设计成本，使其更具实用性：(1)从不同工艺节点制造的模具到通过tsv、硅中间层和线键实现的互连；(2)从系统性能（具有不同频率要求的宏块）到系统活动（备用主导与主动切换的块）；(3)在物理设计层面，从临界性（性能松弛）到连接性（二分带宽或网切），跨越从块级到门级的物理层次结构。我们的研究范围涵盖三个主要方面——3D集成电路实现架构、异构技术和设计方面以及算法优化。能够在一个工作的电子系统中组合异构半导体芯片，在价格、性能和功能上具有显著的竞争优势。这种能力促进了新型电子产品的发展，对设计和制造公司以及社会都有明显的好处。这里的一个示例应用是蜂窝电话，它集成了几个微处理器、模拟电路组件和天线、信号处理单元、加速度计等。能够在不改变其他模块的供应链的情况下修改其中一个模块，可以降低改进成功设计的风险和成本。学生将被训练参与设计和修改这些设计，并对替代芯片设计技术进行进一步的研究。

The dramatic improvements in electronic devices in the last 40 years have substantially drawn on Moore's law which predicts a steady increase in transistor density in semiconductor chips, with implied improvements in cost and power. But Moore's law is now slowing, while cost improvements now rely on very large production volumes to justify billion-dollar in investments in manufacturing infrastructure. Among alternative chip design methodologies, three-dimensional chip design currently shows significant momentum and promise for commercial products. Three-dimensional chips can be produced by vertical stacking of conventional two-dimensional chips and connecting them with through-silicon vias. Despite a number of unsolved technical problems, such three-dimensional chips reduce the form-factor and interconnect, while improving yield. This research explores heterogeneous 3D chip design seeking the flexibility to combine different types of two-dimensional chips (different types of memories, fast logic, low-power logic, FPGAs, analog circuits, micro- and nano-electromechanical components, etc.), which cannot be reliably manufactured on a single conventional die. This research will reduce cost of 3D designs and make them more practical by exploiting heterogeneity in all its aspects: (1) from dies fabricated in different process nodes to interconnects realized with TSVs, silicon interposers and wire bonds; (2) from system performance (macro blocks with different frequency requirements) to system activity (blocks that are standby-dominant vs. actively-switching); and (3) at the physical design level, from criticality (performance slack) to connectivity (bisection bandwidths or netcuts) across the physical hierarchy from block-level down to gate-level. Our research scope spans three main axes -- 3D IC implementation architectures, technology and design aspects of heterogeneity, and algorithmic optimizations. Being able to combine heterogeneous semiconductor dies in a working electronic system promises significant competitive advantage in price, performance and functionality. Such ability facilitates new types of electronic products, with clear benefits to design and manufacturing companies, as well as to the society. An example application here is a cellular phone, which integrated several micro-processors, analog circuit components and antennas, signal-processing units, accelerometers etc. Being able to revise one of these blocks without altering the supply chain for other blocks reduces the risk and cost of improvements to successful designs. Students will be trained to contribute to the design and revision of such designs, and to perform further research on alternative chip design techniques.