SHF: Medium: Energy Efficient Memory Systems

这个项目的目标是开发节能系统。提高能源效率是信息技术面临的一个决定性挑战，也是提高所有计算系统（从智能手机到仓库规模的数据中心）能力的先决条件。该领域的大多数研究都集中在节能计算上，使用专门的核心或近阈值电压电路。为了实现端到端的能效，为内核提供数据和指令的片内和片外存储系统也必须进行优化。存储系统包括大的、泄漏的结构和通信操作，它们带来的能量开销比计算操作的开销要高几个数量级。本计画提出一种朝向节能记忆体系统的整体方法，重新思考记忆体系统架构、动态运行时管理和电路设计。在体系结构级别，它将通过将计算放置在内存结构附近来优化具有有限时间局部性的以数据为中心的新兴应用程序，从而最大限度地减少能源密集型通信。它还将探讨对内存系统专门化的体系结构支持，例如专门化预取、数据转换和数据分发的引擎。在运行时管理层面，它将研究可扩展的调度算法，通过最大化时间和空间局部性以及使用片上和内存端加速器来最大限度地减少内存系统中的能源使用。在电路设计层面，它将在有效的运行时管理之后，积极优化存储芯片和存储堆栈的内部结构的能耗，以适应主流的访问模式。最后，该项目将创建用于共同探索架构-管理-调度空间的工具，以确定不同性能水平的Pareto最优内存系统。

The goal of this project is to develop energy efficient systems. Improving energy efficiency is a defining challenge for information technology and the prerequisite to increasing the capabilities of all computing systems, from smartphones to warehouse-scale data-centers. Most research in this area has focused on energy efficient computing, using specialized cores or near-threshold voltage circuits. To achieve end-to-end energy efficiency, the on-chip and off-chip memory system that feeds cores with data and instructions must also be optimized. The memory system includes large, leaking structures and communication operations that introduce energy overheads orders of magnitude higher than the overheads of compute operations.This project proposes a holistic approach towards energy efficient memory systems that rethinks memory system architecture, dynamic runtime management, and circuit design. At the architecture level, it will optimize for emerging, data-centric applications with limited temporal locality by placing computing close to the memory structures so that energy intensive communication is minimized. It will also explore architectural support for specialization in the memory system, such as engines for specialized prefetch, data transformations, and data distribution. At the runtime management level, it will investigate scalable scheduling algorithms that minimize energy usage in the memory system by maximizing temporal and spatial locality and the use of on-chip and memory-side accelerators. At the circuit design level, it will aggressively optimize the energy consumption of the internal structures of memory chips and memory stacks for the dominant access patterns after efficient runtime management. Finally, this project will create tools for joint exploration of the architecture-management-scheduling space in order to identify Pareto optimal memory systems for different levels of performance.