SHF: Small: Improving Memory Performance on Fused Architectures through Compiler and Runtime Innovations

在过去的十年中，像图形处理单元（gpu）这样的加速器已经进入了通用计算领域。它们现在被广泛用于实现科学模拟、业务分析、图像处理和许多其他应用领域的高性能。然而，它们的有效性在很大程度上受到与多核cpu之间狭窄而缓慢的互连的限制。现代架构不再采用这种一边是多核cpu，另一边是gpu的分离存储器，而是采用集成设计：传统的cpu和辅助加速器集成在同一个芯片上，可以访问相同的存储器。这种集成为cpu和gpu上的协同执行提供了新的机会，但也可能加剧内存层次结构中的资源争用。其含义仍有待理解。该项目旨在系统地探索集成的新挑战和机遇，特别是对于编译器和运行时系统来说，在控制程序转换和在运行时维护它们以实现数据位置、任务划分和调度。pi建议通过促进协同执行来支持数据共享，同时在CPU和GPU执行之间创建隔离范围，以减轻非共享数据的资源争用，从而提高技术水平。所提出的技术包括一组新颖的编译器转换、并发程序控制和数据抽象，以及基于共享硬件资源的内存访问模式促进共享和减少跨界争用的系统机制。编译器技术和运行时系统之间的这种协同作用有可能显著提高在融合架构上协同调度程序片段的性能和功率保证。

During the past decade, accelerators such as Graphics Processing Units (GPUs) have entered the area of general-purpose computing. They are now widely used for achieving high performance in scientific simulation, business analytics, image processing, and many other application domains. Their effectiveness however has been largely constrained by narrow and slow interconnections to multicore CPUs. Instead of such disjoint memories for multicore CPUs on one side and GPUs on the other, contemporary architectures are adopting an integrated design: Conventional CPUs and co-accelerators are integrated on the same die with access to the same memory. The integration provides new opportunities for synergistic execution on CPUs and GPUs, but can also intensify resource contention within the memory hierarchy. The implications yet remain to be understood.This project aims to systematically explore the new challenges and opportunities of the integration, especially for compilers and runtime systems in governing program transformations and maintaining them at runtime for data locality, task partitioning and scheduling. The PIs propose to advance the state of the art by promoting synergistic execution in support of data sharing while creating spheres of isolation between CPU and GPU execution to mitigate resource contention of non-shared data. The proposed techniques include a set of novel compiler transformations, concurrent program control and data abstractions, and systems mechanisms that fostersharing and reduce cross-boundary contention depending on memory access patterns with respect to shared hardware resources. This synergy between compiler techniques and the runtime system has the potential to significantly improve performance and power guarantees for co-scheduling program fragments on fused architectures.