Development of novel system and component architectures for future multichannel 100 GBit/s communication systems (M-SPARS)

超高速无线通信可以通过极高的载波频率来实现。在这种情况下，通常使用具有高指向性的天线配置来达到可接受的信噪比。因此，单通道系统在需要正确对准发射和接收天线的情况下是不灵活的。多天线系统，例如MIMO系统，需要对节点进行寻址，无论方向如何。如今，具有极高载流子频率的收发器基于半导体技术，其工作频率接近于目前可用的最大传输频率。鉴于此，经典的同差收发器因此需要包含多个级的放大器链以及精心设计的正交调制器和解调器；因此，对于构建多天线系统的经典同差方法而言，整体前景的W.R.T.芯片表面积要求和功耗极具挑战性。该项目的目的是研究基于全新类型的收发器架构的100 Gbit/s多通道通信系统的创新构建选项，该架构大大降低了电路复杂性。该项目是SPP 1655项目SPARS的第一阶段的延续，该项目验证了复杂的低噪声和功率放大器链可以被单级开关注入锁定振荡器（SILO）和正反馈再生所取代，并且可以在更低的功率水平和更低的电路复杂性下产生16 QAM调制信号。收发器结构将得到简化和改进，紧凑的多通道架构将在下一个项目阶段设计最佳集成。正交通道，从而一个完整的信号路径，将从接收机中移除，从而也有效地减少了直流，相位和增益失调问题。这是通过25 GHz的中频实现的，采用新型差分解调部分，具有两个同步调制的偏频silo和一个具有40 GHz模拟带宽的100 GS/s a /D转换器。1/4采样率的中频可以有效解调，外差基带可以无缝扩展到多个通道。紧凑的BPSK调制器部署在发射机。调幅是通过项目第一阶段研究的发射井的脉冲宽度调制来实现的。SILO架构现在首次升级为同步调制SILO阵列。在新概念的发射机中也不需要IQ混频器。将开发一个系统模型，为这种新的和大大简化的收发器架构提供理论基础，并研究SILO阵列中的相位抖动和频率漂移等干扰。将为中心频率为180 GHz的两个通道构建完整的发射器和接收器前端，以演示和验证这些概念。

Ultra high-speed wireless communication can be achieved by means of extremely high carrier frequencies. Antenna configurations with high directivity are typically used in this context to reach an acceptable signal-to-noise ratio. Thus, single channel systems are inflexible given the need to correctly align the transmitting and receiving antennas. Multi-antenna systems, e.g. MIMO systems, are needed to address nodes, regardless of direction. Transceivers with an extremely high carrier frequency are nowadays based on semiconductor technologies that operate close to the maximum transit frequency that is available today. Given that, classical homodyne transceivers therefore need amplifier chains comprising several stages as well as elaborate quadrature modulators and demodulators; hence, the overall prospect w.r.t. chip surface-area requirements and power consumption for the classical homodyne approach to build multiple-antenna systems is extremely challenging. The aim of this project is to research, innovative build options for 100 Gbit/s multi-channel communication systems based on an entirely new type of transceiver architecture with drastically reduced circuit complexity. The project is a continuation of the first phase of the SPP 1655 project SPARS, which verified that complex low-noise- and power-amplifier chains can be replaced by the single-stage switched injection-locked oscillator (SILO) and by regeneration with positive feedback, and that 16 QAM modulated signals can be generated at a much lower power level and with lower circuit complexity. The transceiver structure will be simplified and improved and compact multi-channel architectures that are optimally integrable will be designed in the next project phase. The quadrature channel, and thus a complete signal path, will be removed from the receiver, and thereby also the DC-, phase- and gain offset problems are effectively reduced. This is achieved with an IF of 25 GHz, produced with a novel differential demodulation section with two synchronously modulated SILOs with offset frequency and a 100 GS/s A/D converter with 40 GHz analog bandwidth. The IF at 1/4 the sampling rate can be efficiently demodulated and the heterodyne baseband can be seamlessly extended to multiple channels. Compact BPSK modulators are deployed in the transmitter. Amplitude modulation is implemented by a pulse width modulation of the SILO studied in project phase 1. The SILO architecture is now upgraded to synchronously modulated SILO arrays for the first time. There is also no need for IQ mixers in the transmitter in the new concept. A systems model will be developed to provide a theoretical basis for this new and drastically simplified transceiver architecture and to investigate disturbances like phase jitter and frequency drift in the SILO arrays. Complete transmitter and receiver frontends for two channels with a center frequency of 180 GHz will be built to demonstrate and verify the concepts.