FAST - Reliability Assessment using Faster-than-at-Speed Test

最先进的纳米技术允许将数十亿个特征尺寸为14纳米或以下的晶体管集成到单个芯片中。这使得许多应用程序领域中的创新方法和解决方案成为可能，但同时也带来了根本性的挑战。早期故障尤为关键，因为它们可能导致产品召回，造成数十亿美元的损失。早期失效的一个主要原因是在制造测试期间正常运行的弱设备，但不能承受现场的操作压力。虽然其他失效机制，如老化或外部干扰，在某种程度上可以通过健壮的设计来补偿，但必须通过测试来检测潜在的早期寿命失效，并且必须对各自的系统进行分类。这需要远远超出当前技术水平的具体方法。由于它们在开始时正常工作，因此必须通过分析非功能电路行为来识别弱结构，并借助适当的可观测值。除功耗外，电路时序也是最重要的可靠性指标之一。特别是，小的延迟故障可能表明边缘硬件在压力下会进一步退化。然而，它们可以隐藏在标称频率，只有在更高的频率（快于速度测试/ FAST）才能被检测到。因此，传统的测试方法已经达到了极限，必须在以下三个领域研究和开发新方法：a)必须开发用于测试设计（DFT）的特定技术，以应对超出标称频率的测试挑战。b)测试调度策略必须确保以最少的测试频率和较短的测试时间实现最大的故障覆盖。c)需要适当的度量来量化弱设备的覆盖。在这里，将周器件的行为与纳米级集成引起的变化区分开来尤其具有挑战性。由于FAST对自动测试设备（ATE）提出了极高的要求，因此支持作为内置自检（BIST）的有效实现非常重要。在该项目的框架内，将针对上述问题制定战略和解决办法。通过这种方式，可以减少传统老化测试的巨大成本，从而使纳米级技术能够引入新的应用领域。

State-of-the-art nanoscale technologies allow for the integration of billions of transistors with feature sizes of 14 nm or below into a single chip. This enables innovative approaches and solutions in many application domains, but it also comes along with fundamental challenges. Early life failures are particularly critical, as they can cause product recalls associated with a loss of billions of dollars. A major cause of early life failures are weak devices that operate correctly during manufacturing test, but cannot stand operational stress in the field. While other failure mechanisms, such as aging or external disturbances, to some extent, may be compensated by a robust design, potential early life failures must be detected by tests, and the respective systems have to be sorted out. This requires specific approaches far beyond the current state-of-the-art.As they work properly in the beginning, weak structures must be identified by analyzing the non-functional circuit behavior with the help of appropriate observables. Besides power consumption, the circuit timing is one of the most important reliability indicators. In particular, small delay faults may indicate marginal hardware that can degrade further under stress. However, they can be hidden at nominal frequency and only be detected at higher frequencies (faster-than-at-speed test / FAST). Therefore, conventional approaches for testing reach their limitations, and new methods must be investigated and developed in the following three domains:a) Specific techniques for design for test (DFT) must be developed to deal with the challenges of testing beyond nominal frequency.b) Strategies for test scheduling must ensure that a maximum fault coverage is achieved with a minimum number of test frequencies and a short test time.c) Appropriate metrics are needed to quantify the coverage of weak devices. Here it is particularly challenging to distinguish the behavior of week devices from variations due to nanoscale integration.Since FAST imposes extreme requirements on the automatic test equipment (ATE), it is very important to support an efficient implementation as a built-in self-test (BIST). Within the framework of the project, strategies and solutions will be developed for the problems mentioned above. This way, the enormous cost of a traditional burn-in test can be reduced, thus enabling the introduction of nanoscale technology to new application domains.