Unlocking Analog Features and Full Parallelism for HDL-based Synthesis of PLiM

由先进的非易失性存储器技术实现的存储器内计算是当前计算系统中的冯·诺依曼瓶颈的已知问题的有希望的范例。然而，逻辑设计的内存计算能力还没有得到充分的探索。该提案包括六个工作包，这些工作包有助于基于电阻式RAM（RRAM）标准交叉的存储器中逻辑计算机架构的设计自动化的进步和全面性。该研究计划旨在通过创建新的并行能力，基于RRAM固有的模拟计算能力和近似计算开发新功能，来提高电阻式存储器逻辑计算机架构的性能。此外，我们的目标是将这些新元素添加到在项目初始阶段开发的逻辑内存硬件描述语言（LiM-HDL）中。

In-memory computing enabled by advanced non-volatile memory technologies is a promising paradigm for the known issue of von Neumann bottleneck in current computing systems. However, the capacity of in-memory computing for logic design has not been fully explored. This proposal includes six work packages that contribute to the advancement and comprehensiveness of design automation for logic-in-memory computer architectures based on standard crossbars of Resistive RAM (RRAM). This research plan aims at enhancing the performance of resistive logic-in-memory computer architectures by creating new capacity for parallelism, developing new features based on the inherent analog computation capability of RRAM and approximate computing. Furthermore, we aim at adding these new elements to the Logic-in-Memory Hardware Description Language (LiM-HDL), which has been developed in the initial phase of the project.