Research on Logic Synthesis and Hardware Description Language Considering Layout Design
Research on Logic Synthesis and Hardware Description Language Considering Layout Design
批准号:
04452198
负责人:
YASUURA Hiroto
金额:
$4.54万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (B)
财政年份:
1992
资助国家:
日本
项目状态:
已结题
起止时间:
1992 至 1993
中文摘要
传统逻辑综合技术的主要目的是生成逻辑电路的拓扑信息,实现功能描述给出的功能。最终出现在掩模图案中的几何信息是在布局综合阶段独立于逻辑综合阶段确定的。因此,在控制路径等随机电路的情况下,有可能获得比手工设计更好的性能。但是,对于像数据路径这样的规则电路,很难设计出一种好的综合方法,在逻辑综合中考虑布局的几何限制,并为此设计一种描述语言。(a)表征布图模式规律性的设计描述语言研究:提出了一种能够表征布图模式的规律性以及功能设计中布图和布线信息轮廓的语言。(b)考虑面积和布线延迟的逻辑综合研究:研究了逻辑综合中考虑布线延迟和布线延迟的逻辑综合方法,提出了一种利用交换律的电路综合方法。(c)设计实用电路的方法比较:我们检查了几种合成方法的效果,并将它们应用于微处理器的实际开发。我们具体指出了商业工具和语言上的问题。(d)逻辑综合方法的应用:作为我们方法的一个应用,我们提出了使用软核处理器的硬件/软件协同设计。通过以上研究,我们将独立完成的逻辑综合和布局综合统一起来。在该方法中,设计者在建筑设计中指定布局信息,利用这些信息进行逻辑综合和布局综合。给出了一种新型设计自动化系统的框架及其应用方法。
英文摘要
Traditional logic synthesis technology principally aims at generating topological information of logic circuits, realizing function given by functional description. Geometric information which appears in a final mask-pattern is decided in layout synthesis stage independently from logic synthesis. Therefore, in the case of random circuits like control-path, it is possible to get better performance than manual design. But, in the case of regular circuits like data-path, iti is hard to design good synthesis method in which geometric restriction on layout is considered in logic synthesis, and a design description language for that purpose.(a) Study on design description language that canrepresent regularity of layout-pattern : We proposed a language which can specigy the regularity on layout-pattern and the outline of placement and routing information in functional design.(b) Study on logic synthesis considering areas and wiring delays : We investigated a logic sythesis method considering wiring delays and areas in logic synthesis, and proposed a circuit synthesis method using the commutative law.(c) Comparisons of methods to design the practical circuits : We examined the effect of the several synthesis methods, applying them to practical development of a microprocessor. We concretely point out problems on commercial tools and languages.(d) Applocation of the logic synthesis method : As an application of our method, we propose hardware/software codesign using soft core-processor.Through the above researches, we unified logic synthesis and layout synthesis, which have been done independently. In our method, designers specify information on layout in architecture design, and logic synthesis and layout synthesis are done using its information. We also show a framework of new design automation system and its application method.
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安浦 寛人: "ハードウェア設計記述言語の利用状況と今後の動向" 1992年電子情報通信学会春季大会. (1992)
Hiroto Yasuura:“硬件设计描述语言的使用现状和未来趋势”1992 IEICE 春季会议(1992)。
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Hiroki Akaboshi,Hiroto Yasuura: "COACH:A Computer Aided Design Tool for Computer Architects" The Transactions of IEICE. E.76-A. 1760-1779 (1993)
Hiroki Akaboshi、Hiroto Yasuura:“COACH:计算机架构师的计算机辅助设计工具”IEICE 汇刊。
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Moshnyaga,Tamaru,Yasuura: "Design of Data-Path Modules Generators from Algorithmic Representations" Synthesis for Control Dominated Circuits,North-Holland. (1993)
Moshnyaga、Tamaru、Yasuura:“根据算法表示设计数据路径模块生成器”综合控制主导电路,北荷兰。
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Akaboshi,Tomiyama,Yasuura: "Compiler Generation from Hardware Description Language" Proceedings of First Asian Pacific Conference on Hardware Description Languages,Standards & Applications. 76-78 (1993)
Akaboshi、Tomiyama、Yasuura:“从硬件描述语言生成编译器”第一届亚太硬件描述语言、标准会议论文集
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Vasily Moshnyage, Keikichi Tamaru and Hiroto Yasuura: "A Language for Designing Module Generators" The Transactions of LEICE. vol.E.76-D.No.9. 1066-1073 (1993)
Vasily Moshnyage、Keikichi Tamaru 和 Hiroto Yasuura:“设计模块生成器的语言”LEICE Transactions。
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共 13 条
Research on Design Methodology of Dependable LSI Loading Value and Trust
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财政年份:2007
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The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption
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A Study on Delay and Function Test for Core-Based System LSIs
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财政年份:1999
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Research on Low-Power Design of Microprocessor Systems.
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批准号:09480057
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Development of Curriculums for Education of VLSI System Design.
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财政年份:1996
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Research on Performance Evaluation Technology for High-Performance Computer Systems
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资助金额:$4.74万
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财政年份:1995
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Development of Educational Microprocessors for Computer Science Education
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资助金额:$11.58万
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财政年份:1994
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依托单位:
Research on High-Level Information Extraction in Integrated Circuit Design
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批准号:02650264
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财政年份:1990
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负责人:YASUURA Hiroto
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