A Study on Automatic Layout Design System for Deep-Submicron High-Performance VLSI

在本研究中，我们研究了深亚微米VLSI芯片版图设计自动化的新版图设计方法，以解决考虑电路性能、硬/软宏和最小化设计时间的问题。(1)性能驱动的电路划分方法为了优化电路的性能，提出了路径延迟约束下的电路划分算法。(2)性能驱动的楼面规划方法针对硬/软宏的楼面规划设计，提出了一种基于线材尺寸和缓冲区插入的精确估算面积和互连延迟的性能驱动的楼面规划方法，并证明了该方法的有效性。(3)性能驱动的放置方法提出了一种基于细胞聚类的时间驱动的标准细胞放置方法和新的放置模型阿米巴模型。(4)性能驱动的路由方法针对多路由层模型，提出了一种时序驱动的分层全局路由方法，该方法采用带线尺寸和缓冲区插入的Steiner树生成算法。(5)性能驱动的分层缓冲块规划方法我们提出了一种分层缓冲块规划方法，该方法在考虑时序约束的情况下，将芯片区域划分为全局bin。(6)自适应遗传算法在性能驱动布局设计中的应用本文提出了一种基于精英度的自适应遗传算法，并将其应用于布局设计问题。我们还将所提出的GA作为GA加速LSI芯片来实现，以加快执行速度，并获得了性能驱动布局方法高速执行10倍的前景。

In this research, we studied new layout design methods for layout design automation of deep-submicron VLSI chips so as to solve the problems considering the performance of circuits, hard/soft macros, and minimizing of design time.(1) Performance-driven circuit partitioning methodAn circuit partitioning algorithm under path delay constraints was proposed to optimize performance of circuit.(2) Performance-driven floorplanning methodsFor floorplanning design with hard/soft macros, we proposed a performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion and showed effectiveness of the method.(3) Performance-driven placement methodA timing-driven standard cell placement method based on cell-clustering and the new placement model, that is, ameba model was proposed.(4) Performance-driven routing methodsFor multi-routing layer model, we proposed a timing-driven hierarchical global routing method using a Steiner tree generation algorithm with wire sizing and buffer insertion.(5) Performance-driven hierarchical buffer-block planning methodWe proposed a hierarchical buffer block planning method, which divides the chip area into global bins, taking timing constraint into account.(6) Applications of an adaptive genetic algorithm to performance-driven layout designWe newly proposed an adaptive genetic algorithm based on elite degree and applied to the layout design problems. We also implemented the proposed GA as GA accelerator LSI chips to speed up the execution and got a prospect of high-speed execution of number 10 times for performance-driven layout methods.