A Study on How Implementing Microprocessors Exploiting Instruction Level Parallelism

功耗是嵌入式微处理器设计中的一个主要问题。降低功耗也是通用微处理器的一个关键设计目标。由于它们需要高性能和低功耗，因此以性能为代价的功耗降低是不可接受的。有许多设备级技术可以在保持性能的同时降低功耗。他们选择非关键路径作为低功耗设计的候选路径，而面向性能的设计仅用于速度关键路径。同样的理念也适用于架构级设计。我们评估了一种技术，该技术利用关于指令临界的动态信息来降低功耗。关于维持吞吐量对功耗和性能的影响，我们发现，即使考虑到由于额外锁存而增加的硬件，流水线功能单元也比非流水线功能单元在节能和性能方面更好。我们还评估了基于指令临界性的集群微架构的指令转向策略，并发现它目前不是一个很好的能效设计选择。

Power consumption is a major concern in embedded microprocessors design.Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power..Regarding the effect of sustaining throughput on power and performance, it is found that pipelined functional units are better in energy reduction as well as in performance than non-pipelined units even if the increase in hardware due to extra latches are considered. We also evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is currently not a good design choice for energy efficiency.