Study on Built-in Self Test and Fault Diagnosis for Very High Speed and Deep Sub-micron VLSIs

我们开发了一种诊断试验压实方法，一种针对开放故障的故障诊断方法和一种针对内部桥接故障的故障诊断方法。(1)诊断测试压实方法在lsi的内置自检中，必须应用大量的测试向量。我们开发了一种选择少量测试载体用于诊断故障lsi的方法。该方法可以减少故障诊断的执行时间，减少存储测试数据和输出响应的内存空间。该方法在给定的测试集中选择少量的测试向量，从而保留了由给定测试集区分的故障对的数量。首先，提取仅被一个测试向量检测到的故障，并收集检测到该故障的测试向量；然后，选择故障对的子集，并选择少量的测试向量，以便通过测试向量来区分所选的故障对。重复选择故障对和测试向量的过程，直到区分出所有故障对。(2)开路故障的诊断方法我们开发了一种开路故障的诊断方法。在本研究中，我们假设在有开路故障的信号线处的值由相邻的信号线确定。该方法通过通过测试和失败测试进行故障模拟，推导出少量候选故障点。(3)内部桥接故障的故障诊断方法我们开发了一种内部桥接故障的诊断方法，这种故障是由两个晶体管节点之间的短路引起的。该方法首先通过通过测试进行逻辑仿真，提取疑似故障门。然后，推导出疑似故障门存在的疑似内部桥接故障。此外，它还通过使用通过的测试执行逻辑模拟来减少可疑的内部桥接故障。

We have developed a diagnostic test compaction method, a fault diagnostic method for open faults and a fault diagnostic method for internal bridging faults.(1)Diagnostic test compaction methodIn built-in self test of LSIs, a large number of test vectors must be applied. We have developed a method for selecting a small number of test vectors used for diagnosis of faulty LSIs. This method can reduce the execution time for fault diagnosis as well as memory space to store test data and output responses. The developed method selects a small number of test vectors among a given test set so that the number of fault pairs distinguished by the given test set is preserved. First, it extracts faults that are detected by only one test vector, and collect the test vectors that detect such faults. After that, a subset of fault pairs are selected and a small number of test vectors are selected so that the selected fault pairs are distinguished by the test vectors. The process of selection of fault pairs and test vectors is repeated until all the fault pairs are distinguished.(2)Fault diagnostic method for open faultsWe have developed a diagnostic method for open faults. In this research, we assumed that the value at a signal line with open fault is determined by adjacent signal lines. The developed method perform fault simulation using passing tests and failing tests, and deduces a small number of candidate faulty sites.(3)Fault diagnostic method for internal bridging faultsWe have developed a diagnostic method for internal bridging faults, which are caused by short between two transistor nodes. The developed method first performs logic simulation using passing tests in order to extract suspected faulty gates. Next, it deduces suspected internal bridging faults existing in the suspected faulty gates. Moreover, it reduces the suspected internal bridging faults by performing logic simulation using passing tests.