Development of High-performance Low-power Processor Systems

在这项研究中，我们的目标是开发高性能低功耗处理器系统的构建技术，将软件、体系结构和电路技术相结合，如处理器和存储器体系结构、电压控制和硬件软件协同设计。尽管电压、数据路径宽度和流水线深度在过去是不可用的，但我们为专用处理器系统的设计者提供了这些参数的使用。换句话说，本研究试图为在大的设计空间中设计高效的系统提供手段。这种方法是硬件和软件协同设计技术中最先进的一种，各国都在竞争地研究和开发这种技术。我们认为，重要的是给这些特定于应用程序的处理器系统设计者提供指导。在分析程序中变量的最小位宽(有效位宽)后，利用有效位宽对节能处理器或存储器的数据路径宽度进行优化。2)根据低功耗应用的特点动态控制流水线深度。3)动态控制数据总线和存储器访问位，以抑制不在数据路径中传输必要信息的位的功耗。

In this research, we aim to develop constructing techniques for high-performance low-power processor systems, which combine software, architecture and circuit techniques such as processor and memory architectures, voltage control, and hardware software co-design. Although voltage, datapath width, and pipeline depth are not available in the past, we provide use of these parameters for designers of application-specific processor systems. In other words, this research is trying to provide means for designing high effective systems in large design space. This approach is the most progressive one in hardware software co-design techniques that have been researched and developed competitively in countries. We think that it is important to give these guidelines designers of application-specific processor systems. Proposed techniques can be summarized as follows1)After analyzing the minimum bitwidth (effective bitwidth) for variables in programs, the datapath width is optimized for power efficiency processors or memories by using effective bitwidth.2)The pipeline depth is dynamically controlled in consideration of characteristics of applications for low power.3)Data bus and memory access bits are dynamically controlled to suppress power consumption of bits not transferring necessary information in datapath.