Study of Interface Control in Ultra-thin High-k Film on Silicon Substrate

本研究的目标是科学地判断超薄高介电膜在下一代CMOSULSI中应用的可能性。主要研究结果如下：1.对高介电常数材料的高介电常数的起源提出了认识，并构建了高介电常数材料设计的指导原则。(1)远红外吸收分析清楚地给出了高介电常数材料的声子模式。(2)Y或Si掺杂HfO2可以通过相变提高介电常数(~30)。(3)La掺杂可以提高晶化温度和介电常数。(4)从摩尔体积变化和摩尔极化率两方面定量分析了高k介电材料的介电常数，为高k介电材料的设计提供了指导原则2.对高k/Si界面层的理解和控制(1)HfO2/Si界面层的生长被模拟为衬底取向的参数，氧化时间和温度。这一事实说明了高k/Si界面层的生长机制与硅表面氧化有很大的不同。(2)以原子氧为氧化物种，定量构建了界面层生长模型，提出了界面层控制的指导原则。在此基础上，我们尝试论证了亚纳米EOT高k氧化物。虽然界面特性的改善还需要一些优化，但我们已经实现了EOT=0.8 nm的高k栅堆栈，并且与SiO_2情况相比，漏电流降低了5个数量级。此外，还对Ge上的高k介质进行了部分研究，观察到了该系统的新特性，特别是界面层的特性。这一结果为下一代ULSI器件提供了一个新的研究目标。

This research target was to scientifically judge the possibility of usability of ultra-thin high-k dielectric films for next generation CMOS ULSI. Main results obtained are described below.1.Understanding of origin of high dielectric constants of high-k materials proposed and constructing a guiding principle of high-k materials design.(1)Phonon modes of high-k materials have been clearly provided using far-infrared absorption analysis.(2)Y or Si doping into HfO2 can enhance the dielectric constant (〜30) through the phase transformation.(3)La doping can enhance crystallization temperature as well as dielectric constant.(4)The dielectric constants were quantitatively analyzed through both molar volume change and molar polarizability and a guiding principle for designing high-k dielectrics was proposed.2.Understanding and control of high-k/Si interface layer(1)The interface layer growth at HfO2/Si was modeled as parameters of substrate orientation, oxidation time, and temperature. This fact has clarified that high-k/Si interface layer growth mechanism is significantly different from Si surface oxidation.(2)By taking account of atomic oxygen as oxidation species the interface layer growth model was quantitatively constructed and a guiding principle for the interface layer control was proposed.Based upon those results, we challenged to demonstrate sub-nm EOT high-k oxides. Though still some optimization was needed for the interface characteristics improvement, we have achieved high-k gate stack with EOT=0.8 nm and 5 orders smaller leakage current compared to SiO2 case. Thus, the numerical target of this research has been fully achieved.Furthermore, high-k dielectrics on Ge were also partly studied and new features of this system, particularly in the interface layer, have been observed. This result provides us a new research target for the next generation ULSI devices.