High Performance Parallel Processor System Using Three-Dimensional Processor Chip

提出了一种新的共享存储器并行处理系统。我们设计了一个原型系统并对其性能进行了评估。在该系统中，需要共享的数据通过高速多端口环形总线传输到处理器单元（PE）。采用光互连作为高速多端口环总线。采用具有三维结构的节点共享缓存，降低了缓存失命中率，提高了系统性能。性能的提高几乎与PE的数量成正比。我们开发了光互连和三维集成两项关键技术来实现所提出的系统。我们成功地制造出信号传输损耗极低的光波导，仅为0.029dB/cm。我们使用这种长度为5cm的光波导实现了10Gbps的高速数据传输速率。我们还开发了一种新的光束引线键合技术，将光电探测器和VCSEL直接集成到LSI芯片上。我们利用这些技术制作了一个测试模块，通过该光波导连接SRAM缓存存储器，并验证了这些SRAM缓存存储器之间的光数据传输。此外，我们还开发了基于晶圆键合的三维集成技术。我们在世界上首次成功制造了三维堆叠微处理器测试芯片。我们还制作了一个具有十层存储器的三维堆叠存储器测试芯片。此外，我们开发了一种新的三维集成技术，称为超级芯片集成技术，旨在实现微处理器和存储芯片堆叠的更先进的系统。通过超级芯片集成，我们可以堆叠不同芯片尺寸和厚度的各种芯片。

A new parallel processing system with shared memories was proposed. We designed a prototype system and evaluated its performance. Data to be shared are transferred to processor elements (PE's) through a high-speed multiport ring bus in this system. An optical interconnection is used as the high-speed multiport ring bus. The system performance was improved by using node-shared cache memories with three-dimensional structure which decreases the cache miss-hit rate. The performance increased almost in proportion to the number of PE.We developed two key technologies of optical interconnection and three-dimensional integration to realize the proposed system. We succeeded in fabricating the optical waveguide with an extremely low signal propagation loss of 0.029dB/cm. We achieved a high-speed data transfer rate of 10Gbps using this optical waveguide with the length of 5cm. We also developed a new beam-lead bonding technology to directly integrate photodetectors and VCSEL's on LSI chip. We fabricated a test module using these technologies in which SRAM cache memories were connected by this optical waveguide and confirmed the optical data transfer among these SRAM cache memories.Furthermore, we developed a three-dimensional integration technology based on wafer bonding. We succeeded in fabricating a three-dimensionally stacked microprocessor test chip for the first time in the world. We also fabricated a three-dimensionally stacked memory test chip with ten memory layers. In addition, we developed a new three-dimensional integration technology called a super-chip integration technology aiming to realize a further advanced system with stacked microprocessor and memory chips. We could stack various kinds of chips with different chip size and thickness by the super-chip integration.