Dynamic delay fault testing of high-performance digital circuit in deep submicron technology

在过去的30年里，积极的工艺扩展一直是数字cmos电路设计的主流。它导致了多千兆赫兹集成电路(IC)的设计和前所未有的集成度。现代集成电路的时钟频率超过3 GHz，其芯片包含近3亿个晶体管。数字集成电路的性能一直遵循摩尔定律，每年提高30%。然而，ATE的性能每年只提高了12%。ATE边缘放置精度和被测电路(CUT)性能之间的差异将使未来深亚微米技术(DSM)的全速逻辑测试变得越来越困难。目前大多数先进的延迟故障算法能够传播导致逻辑或毛刺故障的延迟故障，但我们提出了一种深亚微米门延迟故障诊断方法，该方法通过一系列注入和评估来传播实际时序故障和最终产生逻辑故障到初级输出的延迟故障。与回溯算法不同的是，回溯算法通过跟踪故障输出端的伴随式返回电路来预测故障位置，该方法通过将九值电压模型映射到五值电压模型之上来从故障位置传播故障。在这种正向方法中，精度要高得多，因为同时考虑了所有故障输出的所有合成征兆。结果表明，即使在时延相对较小的情况下，所提出的方法也具有较强的鲁棒性和适用性。实验结果表明，该方法产生的故障候选数量是相当多的。

Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. It has resulted in the design of multi-gigahertz integrated circuit (IC) and unprecedented levels of integration. Modern integrated circuits operate at clock frequencies of more than 3 GHz, and their dies contain close to 300 million transistors. Digital IC performance has followed Moore's law, improving annually by 30%. However, ATE performance has improved by only 12% annually. The discrepancy between ATE edge placement accuracy and circuit under test (CUT) performance1 will make at-speed logic testing increasingly difficult for future deep-submicron technologies (DSM).Most of today's advanced delay faults algorithms are able to propagate those delay faults which are creating logic or glitch faults, but we propose an approaches for gate-delay fault diagnosis in deep sub-micron by a series of injections and evaluations to propagate the actual timing faults as well as those delay faults that eventually creating logic faults to the primary outputs. Unlike the backtrack algorithm that predicts the fault site by tracing the syndrome at a faulty output back into the circuit, this approach propagate the fault from fault site by mapping a nine-valued voltage model on top of a five-valued voltage model. In such a forward approach, the accuracy is much higher because all the composite syndromes at all faulty outputs are considered simultaneously. As a result, the proposed approach is robust and applicable even when the delay size is relatively small. Experimental results show that the number of fault candidates produced by this approach is considerable.