A unified congestion driven power aware methodology for VLSI physical design automation

集成电路在芯片和电路板上的布局（物理设计）是VLSI电路设计中众多相互关联的复杂任务之一。设计自动化领域研究的主要部分是致力于开发支持电路布局的高效且易于使用的系统。今天的嵌入式系统包含微处理器，存储器和专用集成电路（ASICS）形式的不同组件的各种组合。如果没有先进和合适的CAD工具，包括物理设计自动化，所有这些都无法实现。超大规模集成电路的互连延迟已成为决定电路性能的关键因素。在高性能处理器和片上系统的设计早期，了解互连对速度和功耗的影响似乎变得越来越重要。因此，电路布局开始在当今的芯片设计中发挥更重要的作用。工艺技术的进步正在推动通信、计算和传感器技术在单一硅衬底上的融合——片上系统（SoC）。SoC将改变未来民用/军用系统的概念化和设计方式。这一发展为电子公司创造的机遇是显而易见的，但这些可能性也带来了必须解决的重大设计问题和必须解决的重大挑战。建议的方法力求达到以下里程碑：(i)将基于数学的方法与先进的元启发式方法相结合，有效地解决片上系统电路布局中潜在的硬优化问题，（ii）通过利用分层/多级优化方法降低与片上系统设计相关的巨大复杂性，（iii）通过早期考虑和在物理设计子问题中解决低功耗设计问题。（iv）加速使用特殊硬件加速器开发的算法，用于分区、放置和路由。

The layout of integrated circuits on chips and boards (physical design) is one of many interrelated complex tasks in VLSI circuit design. A major portion of the research in the area of design automation has been devoted to the development of efficient and easy-to-use systems that support circuit layout. Today's embedded systems contain various combinations of different components in the form of microprocessors, memories and application specific integrated circuits (ASICS). All this cannot be achieved without advanced and suitable CAD tools including physical design automation. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. It seems to become more and more important to know the impact of interconnection on speed and power consumption early in the design trajectory of high-performance processors and Systems-on-Chip. As a  result, circuit layout is starting to play a more important role in today's chip designs.Advances in process technology are driving the convergence of communication, computing, and sensor technologies onto a single silicon substrate -- Systems on a Chip (SoC). SoC will change the way future civilian/military systems are conceptualized and designed. Opportunities created by this development for electronic companies are clear, but with these possibilities also come significant design issues that have to be addressed and grand challenges that must be solved. The proposed approach seeks to achieve the following milestones: (i) integrate mathematical based methods with advanced meta-heuristics to solve the underlying hard optimization problems in circuit layout for Systems-on-Chip effectively and efficiently, (ii) reduce thetremendous complexity associated with System-on-Chip design by utilizing hierarchical/multilevel optimization approaches, (iii) tackle the low power design problem by considering it early and within physical design sub-problems, (iv) speedup the algorithms developed using special hardware accelerators for partitioning, placement and routing.