A study of the challenging issues in 3D-IC technologies
A study of the challenging issues in 3D-IC technologies
批准号:
437575-2012
负责人:
Chen, Li
金额:
$2.91万
依托单位国家:
加拿大
项目类别:
Collaborative Research and Development Grants
财政年份:
2012
资助国家:
加拿大
项目状态:
已结题
起止时间:
2012-01-01 至 2013-12-31
中文摘要
三维(3D)集成已经成为一种潜在的解决方案,可以克服芯片性能、功耗和封装外形的障碍。通过使用直通硅通孔(TSV),硅芯片可以垂直堆叠和互连,从而实现了器件集成的新维度,并显著提高了器件密度。然而,与3D IC技术相关的两个主要可靠性问题。其一是TSV中金属与周围硅的热膨胀系数(CTE)失配,导致连接失效。另一个问题是3DIC中高频信号的性能下降。衬底中TSV和互连线之间的耦合对高频信号质量有重要影响。人们试图研究和表征这些影响。然而,该领域开发的仿真模型大多侧重于单个元件的分析,而不是全芯片/封装的分析,并且没有得到实验测量的验证。在本研究项目中,我们建议使用校准模型和实验方法来研究3D全芯片/封装的可靠性问题。3D IC测试芯片将由产业合作伙伴和申请者共同准备。将开发各种专用测试结构,并将其放置在测试芯片中,以研究应变和高频性能。VEPERS光束线上的硬X射线显微衍射(XRD)设备、加拿大光源(CLS)和萨斯喀彻温省结构科学中心(SSSC)的拉曼显微光谱(µRS)设备将用于对测试样品中的应变进行实验研究。拟议中的项目将使加拿大公司在不牺牲可靠性性能的情况下充分利用3D IC技术的优势。同时,它将加强萨斯喀彻温省大学研究小组的能力和专业知识。在项目期间,两名博士和一名暑期学生将参与拟议的合作研究项目,这将使学员能够发展理论和实验方法,以解决来自行业的挑战性问题。
英文摘要
Three-dimensional (3D) integration has emerged as a potential solution to overcome the obstacles on chip performance, power dissipation and packaging form factor. Silicon chips can be vertically stacked and interconnected with the use of through silicon vias (TSVs), which enables a new dimension for device integration and significantly increases device density. However, there are two major reliability concerns associated with the 3D IC technologies. One is caused by the coefficient of the thermal expansion (CTE) mismatch between the metal in TSV and surrounding Si, which will lead to connection failures. The other one is the performance degradation of high frequency signals in 3D ICs. The coupling among TSVs and interconnects in the substrate can significant affect the high frequency signal quality. Attempts have been made to study and characterize these effects. However, most of the simulation models developed in this field were focused on analyzing individual elements instead of full-chip/package, and were not validated with experimental measurements. In this research project, we propose to study the reliability issues in 3D full-chip/package using calibrated models and experimental approaches. 3D IC test chips will be prepared by the industrial partner and the applicants. Various dedicated test structures will be developed and placed in the test chip to study the strain and high frequency performance. The hard X-ray micro-diffraction (XRD) facility at the VEPERS beamline, Canadian Light Source (CLS) and the Raman micro-spectroscopy (µRS) equipment at the Saskatchewan Structural Science Centre (SSSC) will be used to experimentally study the strain in the test samples. The proposed project will enable Canadian companies fully take the advantages of the 3D IC technologies without sacrificing the reliability performance. At the same time, it will enhance the capability and expertise of the research group at the University of Saskatchewan. During the project period, two Ph.D. and one summer students will participate in the proposed collaborative research project, which will enable the trainees to develop both theoretical and experimental methods to solve the challenging problems from industry.
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