Achieving predictability, repeatability and performance for hard real-time embedded systems

为了在硬实时嵌入式计算（HRTEC）中使用芯片多处理器（CMP），我们需要创新计算机体系结构技术，以展示可预测和可重复的计时行为，并同时提高性能。这是因为HRTEC将及时性作为正确性的标准，确保始终满足时间要求是至关重要的。通过准确的最坏情况执行时间（WCET）分析来确保这些定时需求。不幸的是，现代单处理器和CMP架构的设计观点是越快越好；因此，采用推测执行、缓存一致性协议和尽力而为路由等体系结构技术。结果设计不太适合HRTEC，因为WCET分析要么需要巨大的努力，要么就是难以处理。此外，这种设计不能扩展到CMP架构。

In order to use chip-multiprocessors (CMP)s for hard real-time embedded computing (HRTEC), we need to innovate computer architectural techniques that exhibit predictable and repeatable timing behaviours, and those that simultaneously enhance performance. This is because HRTEC makes timeliness a criterion for correctness, and ensuring that timing requirements are always met is of critical importance. These timing requirements are ensured through accurate worst-case execution time (WCET) analysis. Unfortunately, modern uniprocessors and CMP architectures are designed with the perspective that faster is always better; thus, employing architectural techniques such as speculative execution, cache-coherency protocols, and best-effort routing. The resulting designs are poorly suited to HRTEC because WCET analysis either requires heroic efforts or is just intractable. In addition, such designs do not scale to CMP architectures.