Heterogeneous manycore accelerator architectures

最近半导体技术缩放的不连续性已经导致具有集成在单个硅芯片上的许多计算“核心”的系统的广泛发展。 随着每个芯片的核心数量的增加，一些核心被专门化变得很重要，当与增加的并行性相结合时，将使这些系统的有效编程成为一个挑战。 这样的系统的示例包括集成了数百个可经由对C/C++编程语言的扩展来编程的简单核的当代图形处理器（GPU），以及集成了常规（CPU）计算核与类似GPU的加速器核的AMD Fusion微处理器。 该研究计划的目标是探索新的硬件架构，以更低的成本提供更高的计算性能，同时简化软件开发过程。 该方案包括两个综合调查路线。 第一个重点是新的并行芯片microachitectures和第二个重点是开发分析建模技术，快速预测这些架构上的应用程序的性能。 我们在第一条调查线的假设是并行软件开发可以通过新的架构来简化，这些架构可以弥合目前存在于高端台式机和服务器计算机中的高单线程性能支持与当前图形处理器（GPU）中的极端并行性支持之间的鸿沟。 我们在第二条调查线中的假设是，随着我们达到半导体扩展的极限，性能调优将消耗越来越多的软件开发人员时间，并且可以通过使用分析建模来识别性能瓶颈来减轻开发人员的工作。 加拿大将从这一研究中受益，因为它将降低计算机硬件和软件开发成本，并通过领导异构并行硬件系统的创新，加强其在全球信息技术产业中的地位。

Recent discontinuities in semiconductor technology scaling have led to the widespread development of systems with many computing "cores" integrated on a single silicon chip. As cores per chip increase it becomes important for some of the cores to be specialized, which when combined with increasing parallelism will make effective programming of these systems a challenge. Examples of such systems include contemporary graphics processors (GPUs) integrating hundreds of simple cores programmable via extensions to the C/C++ programming languages and the AMD Fusion microprocessor that integrates regular (CPU) computing cores with GPU-like accelerator cores. The objective of this research program is to explore novel hardware architectures that deliver higher computing performance at lower cost while simultaneously simplifying the software development process. The program comprises two integrated lines of inquiry. The first focuses on novel parallel chip microachitectures and the the second focuses on developing analytical modeling techniques for rapidly predicting the performance of applications on these architectures. Our hypothesis in the first line of inquiry is parallel software development can be simplified via novel architectures that bridge the chasm that currently exists between support for high single thread performance as found in high end desktop and server computers and the support for extreme amounts of parallelism found in current graphics processors (GPUs). Our hypothesis in the second line of inquiry is performance tuning will consume a growing proportion of software developer time as we reach the limits of semiconductor scaling and developer effort can be mitigated by using analytical modeling to identify performance bottlenecks. Canada stands to benefit from this research through a reduction in computing hardware and software development costs and by strengthening its presence in the global information technology industry by leading in innovation of heterogeneous parallel hardware systems.