Emerging devices integration above CMOS circuit

在过去的50年里，微电子工业已经能够大幅提高计算性能，同时降低每个芯片的成本。这种突出的改进主要是由于CMOS（互补金属氧化物半导体）技术的缩放。国际半导体技术路线图（ITRS）预计，这一趋势或其性能将持续数年，最终在2025年达到5- 7nm栅极晶体管。这一预测挑战了利用CMOS物理操作晶体管的最乐观预测。因此，必须在中期为后cmos技术引入创新的解决方案。此外，组装模块的功率密度趋势已达到标准风冷无法满足的水平。能源消耗问题正成为引进新设备的主要因素。业界正在寻求不同的方法来实现后cmos和等效的性能增强。对于前一个问题的一个解决方案是引入非常有前途的隧道场效应晶体管。对于后者，已经投入了巨大的努力，通过芯片级的3D集成来增加mm2的设备数量。这项研究计划将通过研究创新的低功耗纳米电子器件来解决这两个问题，这些器件可以用CMOS技术在3D中单片集成，以研究新的功能并提高逻辑和存储器件的性能。总体目标不是直接取代CMOS技术，而是使用后端兼容器件对其进行补充。这种方法允许i)由于3D集成而增加设备密度，ii)减少较短互连的延迟，iii)通过减少寄生损耗在全球范围内降低能耗。在这个5年的项目中，我们将开发两个集成在CMOS电路之上的低功耗纳米电子器件。硅纳米晶隧道场效应晶体管结合了我们的纳米化工艺和非晶硅。这种器件的潜在结果将是实现低功率晶体管工作在低于0.5V的电压下，由于在未掺杂的通道中穿隧而具有极低的关断电流。第二个纳米电子器件也将我们的纳米damascene工艺与氧化铟纳米晶体相结合，以实现嵌入式非易失性存储器。这种双端存储器具有高度可扩展性和嵌入微处理器的潜力。这项研究的科学和社会影响范围从更节能的便携式电子产品（平板电脑，智能手机）到通用存储器（单一存储器类型重组DRAM，硬盘和闪存）。

During the last 5 decades, the microelectronic industry has been able to drastically increase the computing performance while reducing the cost-per-chip. This outstanding improvement is essentially due to the scaling of the CMOS (Complementary Metal Oxide Semiconductor) technology. The International Technology Roadmap for Semiconductors (ITRS) anticipates that this trend or his equivalent in performance will continue for several years resulting ultimately in 5-7 nm gate transistors by 2025. This projection challenges the most optimistic prediction of transistor utilizing the CMOS physics for operation. Thus, innovative solutions must be introduced for post-CMOS technology in the midterm. Furthermore, the power density tendency of assembled modules is reaching level where standard air cooling is not adequate anymore. This energy consumption issue is becoming the predominant factor for introducing new devices. The industry is pursing different approaches for post-CMOS and equivalent performance enhancement. One solution for the former issue is the introduction of the very promising tunnel field effect transistor. For the latter one, tremendous effort have been deployed to increase the number of device by mm2 through 3D integration at the chip level. This proposed research program will address both issues by investigating innovative low-power nanoelectronics device that can be monolithically integrated in 3D with CMOS technology to investigate new functionalities and increase performance of logic and memory devices. The global objective is not to directly replace CMOS technology but rather complement it using back-end-of-line compatible devices. Such approach allows to i) increase devices density due to 3D integration, ii) reduce latency from shorter interconnections, iii) globally reduce energy consumption by reducing parasitic loss. During this 5 years project, we will develop two low-power nanoelectronic devices integrated above CMOS circuit. The silicon nanocrystal tunnel field effect transistor combines our nanodamascene process and amorphous silicon. The potential outcome of such device will be the realization of a low-power transistor operating at voltage below 0.5V with extremely low Ioff current due to tunneling through undoped channel. The second nanoelectronic device will also combine our nanodamascene process with indium oxide nanocrystals to realize embedded non-volatile memory. This two terminals memory has the advantage to be highly scalable and the potential to be embedded with microprocessor. The scientific and social impact of this research is ranging from more energy efficient portable electronic (tablet, smart phone) to universal memory (single memory type regrouping DRAM, hard-disk and flash memory).