Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware

晶体管比例扩大的影响随处可见。通常使用尽可能小的晶体管来降低功率、能量消耗，并增加堆积密度。尺寸越小的晶体管对工艺变化的敏感度越高。因此，实现健壮、可靠的电路设计成为一项挑战。特别是，SRAM电路和低功率、低电压数字电路由于可能的最小晶体管尺寸和低电源电压要求而表现出更高程度的变化。在这项研究中，我们将研究在功率和电压受限的环境中，数字和SRAM电路的可变性感知设计。在微处理器中，多达70%-80%的晶体管位于SRAM中。因此，片上系统(SoC)的各个方面--功率、能量、产量、质量和可靠性都会受到SRAM的影响。

Impact of transistor scaling are evident everywhere. Often small as possible transistors are used to reduce the power, energy consumption, and to increase the packing density. Transistors with smaller dimensions exhibit a higher susceptibility to process variation. As a result, realization of robust, reliable circuit design becomes a challenge. In particular, SRAM circuits, and low-power, low-voltage digital circuits show higher degree of variation owing to smallest possible transistor dimensions, and low-supply voltage requirements. In this research, we will investigate variability-aware design of digital and SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) – power, energy, yield, quality, and reliability are influenced by SRAMs.