Algorithms and Architectures for Digital Communications

本研究的中心主题是无线基带通信系统的算法、并行VLSI架构和片上系统（SoC）实现，以及某些类型的网络连接的前端加密安全硬件。在新兴无线技术领域，很少有技术比CMOS SoC实现在提高成本和性能方面更有希望，CMOS SoC实现具有重要的集成嵌入式内存子系统，这些子系统在算法和架构级别共同设计，以利用所需的矩阵矢量算法的并行结构。*******本研究的目标是开发低复杂度的无线基带信号处理算法和同态加密算法，这些算法既具有良好的性能，又具有高效的微电子实现。解决这一研究挑战的一种方法是，最近在为支持多gb /s性能的低时钟速率嵌入式内存准循环低密度奇偶校验（LDPC）解码器重新制定并行算法方面取得了非常有希望的进展。我们计划在802.11ad兼容的准循环LDPC CMOS原型中进一步开发这些概念，尽管这些概念对其他应用非常有吸引力。例如，我们的并行准循环LDPC算法可以实现基于gpu的块大小为10^6的实现，用于连续变量量子密钥分发（CVQKD）协议，大大提高了当前的能力。******随着嵌入式存储器现在在该领域的SoC系统的面积和成本中占主导地位，我们通过开发LDPC和FFT引擎实现的新见解来进一步推进我们的研究，这些引擎利用了实现的基于内存的性质，但在系统，算法和架构层面上进行了共同设计，从而提高了性能。******完全同态加密（FHE）是最近开发的一种数学技术，它允许对加密的数字进行数学运算（乘法和加法）。作为未来实际实现的核心，密文乘法运算对于几乎所有预期的应用程序都至关重要，尤其是需要搜索和匹配字典很大的应用程序。因此，使用基于中国剩余定理（CRT）和基于嵌入式存储器的创新，更快的多项式乘法技术，有望提高执行时间将被研究。此外，将设计、制造和测试在面积和功率效率高的VLSI实现背景下的架构和电路设计创新，以展示实际应用。******这项工作将影响未来娱乐、教育和商业无线系统的设计和实施方式，提高传输下一代数据、视频和安全信息服务的无线系统的成本和性能。

The central theme of the proposed research is algorithms, parallel VLSI architectures and system-on-chip (SoC) implementations of wireless baseband communication systems and certain types of network-connected head-end cryptographic security hardware. In the domain of emerging wireless technologies few, if any, technologies hold more promise at improving cost and performance than CMOS SoC realizations with significant integrated embedded-memory subsystems that are co-designed at the algorithm and architecture levels to exploit the parallel structure of the matrix-vector algorithms required.*******The goal of this research is to develop low-complexity signal processing algorithms for wireless baseband and homomorphic encryption algorithms that have both provably good performance and an efficient microelectronic realization. A methodology to address this research challenge lies in very promising recent progress in reformulating parallel algorithms for low clock rate, embedded-memory Quasi-Cyclic Low-Density Parity-Check (LDPC) decoders that support multi-Gb/s performance. We plan to further develop the concepts in an 802.11ad compliant Quasi-Cyclic LDPC CMOS prototype, though the concepts are very attractive for other applications. For example, our parallel Quasi-Cyclic LDPC algorithm would enable GPU-based realizations with block sizes of 10^6 for use in Continuous-Variable Quantum Key Distribution (CVQKD) protocols advancing current capabilities significantly. ******With embedded memory now dominating the area and cost of SoC systems in this domain, we further advance our research by developing new insights into the realization of LDPC and FFT engines that exploit the memory-based nature of the implementation but are co-designed at the system, algorithm and architecture levels with improved performance.******Fully Homomorphic Encryption (FHE) is a recently developed mathematical technique that allows mathematical operations (both multiplication and addition) on encrypted numbers. Central to practical future realizations, ciphertext multiplication operations are crucial for almost every envisioned application and especially applications that require searching and matching where dictionaries are large. Therefore, faster polynomial multiplication techniques, using Chinese Remainder Theorem (CRT)-based and embedded memory-based innovations, promising improved execution times will be investigated. Furthermore, architecture and circuit design innovations in the context of area and power-efficient VLSI implementations will be designed, fabricated and tested to demonstrate practical applications.******This work will impact the way future wireless systems for entertainment, education and commerce are designed and implemented improving the cost and performance of wireless systems that transport next generation data, video and secure information services.