Integrated Circuits for Large Arrays

计算和数据通信改变了我们的工作、交流、社交、学习和教育方式。为了改善生计并解决人类社会面临的大多数挑战性问题，我们需要无线连接，计算和数据中心，这些数据中心可以处理大量数据，并具有可持续的功耗。随着互补金属氧化物半导体（CMOS）技术的指数级扩展由于制造中的物理和经济限制而结束，多核和互连数据处理和通信已经脱颖而出。5G蜂窝系统目前采用了10-100个天线阵列，称为大规模MIMO（多输入多输出），以促进通信和计算系统所需的数据吞吐量。此外，下一代架构预计将使用数百到数千个超大型天线阵列，以满足对高速连接的预期需求。这些硬件系统的设计具有非常大的挑战，100-1000个这样的天线需要同步和以精确角度操纵信号的能力（波束成形）。我们的研究将寻求设计电路和系统来解决这样一个网络中的两个关键问题：（1）高频时钟生成，分配和低功耗天线元件之间的同步;以及（2）精确的波束成形。 移动大量数据的类似需求也在出现，以促进大型机器学习计算任务，从而导致采用多个相互连接的加速器芯片，称为小芯片。由于许多机器学习任务依赖于数据密集型的深度神经网络，因此预计未来将有大量的小芯片阵列来执行这些要求苛刻的任务。除了由处理元件执行的数据处理之外，处理如此大的阵列中的数据移动的互连将消耗大量的功率，甚至充当许多任务的显示器。该研究提案将寻求设计电路和系统来解决大型小芯片阵列之间的互连挑战：（1）在没有功率开销的情况下，将短距离电线链路上的数据吞吐量加倍;以及（2）降低硅光子链路的功耗，以便使光学器件更接近计算小芯片。申请人之前的发现资助为这些目标在器件和电路层面奠定了基础。该建议旨在显著降低功耗和增加吞吐量，以实现大型阵列。加拿大是无线通信和机器学习研究的温床。确保我们在硬件研发方面保持领先，以支持下一代蜂窝系统和机器学习加速，将为高价值的工作、技术和初创公司铺平道路。

Computing and data communications have changed the way we work, communicate, socialize, learn, and educate. To improve livelihoods and to solve most of the challenging problems humans face as a society, we need wireless connectivity, computing, and data-centers that can process massive amounts of data with sustainable power consumption. With the exponential scaling of complementary metal-oxide-semiconductor (CMOS) technology coming to an end due to physical and economic limitations in manufacturing, multi-core and inter-linked data processing and communication have risen to the fore. 5G cellular systems have currently adopted 10-100 of antenna arrays, called Massive MIMO (Multiple-Input Multiple-Output), to facilitate the data throughput demanded by communications and computing systems. Furthermore, the next-generation architecture is predicting the use of extremely-large antenna arrays, in hundreds to thousands, to meet the projected demand for high-speed connectivity. The design of these hardware systems has extremely large challenges, with 100-1000 of such antennas requiring synchronization and an ability to steer the signal with precise angles (beamforming). Our research will seek to design circuits and systems to solve two critical problems in such a network: (1) high-frequency clock generation, distribution, and synchronization between the antenna elements with low-power consumption; and (2) precise beamforming. A similar need to move a massive amount of data is also arising to facilitate large machine learning computing tasks, leading to the adoption of multiple accelerator chips, called chiplets, interconnected to each other. With many machine learning tasks relying on data-intensive deep neural networks, large arrays of chiplets are being envisioned to carry out such demanding tasks in the future. Beyond the data crunching carried out by the processing elements, a large amount of power will be consumed by interconnects handling the data movement in such large arrays, even acting as a show-stopper for many tasks. This research proposal will seek to design circuits and systems to solve the interconnect challenge between the large arrays of chiplets: (1) doubling the data throughput on the short-reach electrical wireline links without power overhead; and (2) reducing the power consumption of silicon photonics link so as to bring optics closer to the compute chiplets. The applicant's previous discovery grant laid the foundation for these objectives at the devices and circuits level. This proposal aims for significant power consumption reduction and throughput increase to realize large arrays. Canada is a hotbed for research in wireless communications and machine learning. Ensuring that we also remain ahead in the hardware research and development to support the next generation of cellular systems and machine learning acceleration will pave the way for highly valued jobs, technologies, and startups.