Functional VLSI Module-based Multiprocessor Architectures for Real-time Vision

本项目主要研究超大规模集成电路功能模块的系统集成 通过在它们的界面行为中创造一致性。 这种结合 旨在设计灵活、实时、低级的视觉系统 使用对应于各个操作的模块的流水线。 在这项研究中解决了两个任务。 一、功能模块 为基准视觉操作的设计和特点。 重点放在保持控制的不变性， 输入/输出要求， 每一个操作。 二是静态算法及相关软件 将给定的操作序列映射到一组泛函上 开发了通过交换节点网络连接的模块。 这些算法平衡模块的工作负载，以便 实现高吞吐量。 单个VLSI的特性 模块在操作特定的输入/输出，缓冲区大小， 存储器大小允许对系统性能的更现实的预测。 用于视觉的多处理器架构可分为 同构架构和异构架构。 在 同构体系结构，最佳地利用并行性， 多元化经营在视觉上是非常困难的，而在 异构体系结构，只有一小部分低级操作， 与手头的特定视觉应用相关的是 切实贯彻 这项研究解决了一个重要问题， 开发功能模块及其集成， 根据计算机体系结构动态调整视觉操作， 运行时间。 这项研究的成功可以更好地利用 低级别和高级别视觉操作的并行性。

This project focuses on system integration of VLSI functional modules by creating uniformity in their interface behavior. Such integration is aimed at designing flexible, real-time, low-level vision systems using pipelining of modules that correspond to individual operations. Two tasks are addressed in this research. First, functional modules for benchmarking vision operations are designed and characterized. Emphasis is placed on maintaining invariance in control and input/output requirements with respect to changes in the parameters of each operation. Second, algorithms and associated software for static mapping of a given sequence of operations on a set of functional modules connected through a network of switching nodes are developed. These algorithms balance the workload of the modules in order to achieve high throughput. The characterization of individual VLSI modules in terms of operation-specific input/output, buffer sizes, and memory size allows more realistic prediction of system performance. Multiprocessor architectures for vision can be classified as homogeneous architectures and heterogeneous architectures. In homogeneous architectures, exploiting parallelism optimally for the diversified operations in vision is very difficult, while in heterogeneous architectures, only a small set of low-level operations, relevant to the particular vision applications at hand, are implemented. This research addresses the important problem of developing functional modules and their integration in order to dynamically tailor vision operations to the computer architecture at run time. Success in this research allows better exploitation of parallelism for both low-level and high-level vision operations.