Planning Meetings for the Industry/University Cooperative Research Center for Silicon Wafer Engineering and Defect Science (Si WEDS)

摘要 提案：北卡罗来纳州州立大学硅晶片缺陷工程产学研合作研究中心规划拨款 主要研究者：乔治A. Rozgonyi，NCSU项目官员：Cheryl Cathey日期：1997年3月10日 硅晶片是制造集成电路的基础。 为了在集成电路工业中具有竞争力，硅芯片制造商必须不断努力减小集成电路的部件的特征尺寸。 更小的特征尺寸使芯片制造商能够制造更小的芯片，满足市场对更小电子产品的需求，并提高每个硅晶片的芯片产量，降低每个芯片的成本。 为了确保高产量的高质量芯片，基础材料，硅晶片，必须尽可能没有体和表面缺陷和瑕疵。 该中心将与硅晶片制造商合作：* 为晶片制造社区的研究问题提供一种机制，由学术界确定和解决，* 教育研究生和研究生成为晶片制造研究社区的有效成员，以及 * 提供行政基础设施，以便为大规模晶片缺陷研究中心提供资金。 该中心的研究将分为三个重点：体缺陷和缺陷，表面缺陷和缺陷，以及交叉领域，如计量和模拟。 体缺陷和缺陷推力涉及到对硅晶体成核、生长、运动和湮灭控制的研究。 表面缺陷推力将研究控制和工程晶片表面特性的方法。 交叉领域的重点将侧重于计量发展和计量工具的基本知识。 该中心将由北卡罗来纳州州立大学的乔治罗兹戈尼博士和斯坦福大学的罗伯特赫尔姆斯担任共同主任，并将涉及来自亚利桑那大学、亚利桑那州立大学、南佛罗里达大学、麻省理工学院和伯克利分校的研究人员。 目前有六家晶圆制造公司愿意每年支付5万美元成为该中心的一部分。 凭借这七所大学的研究专长，该中心将帮助晶圆供应商提高其硅片质量，从而使他们能够更好地满足其客户（硅片制造商）的市场需求。 芯片制造商将能够生产更小，更便宜的设备，使他们在电子市场上更具竞争力。

ABSTRACT Proposal: Planning Grant for an Industry/University Cooperative Research Center for Si Wafer Defect Engineering at North Carolina State University Principal Investigator: George A. Rozgonyi, NCSU Program Officer: Cheryl Cathey Date: 10 March 1997 Silicon wafers are the foundation for building integrated circuits. In order to be competitive in the integrated circuit industry, silicon chip manufacturers must continually strive to decrease the feature size of the components of the integrated circuits. A smaller feature size enables the chip manufacturers to both make smaller chips, fulfilling the market demand for ever smaller electronics, and to increase the yield of chips per silicon wafer, decreasing the cost per chip. In order to ensure high quality chips in high yields, the base material, the silicon wafer, must be as free from bulk and surface defects and imperfections as possible. This proposed Center would work with the silicon wafer manufacturers to: * provide a mechanism for the research issues of the wafer manufacturing community to be identified and addressed by the academic community, * educate graduate and post-graduate students to become effective members of the wafer manufacturing research community, and * provide a administrative infrastructure to enable funding of a large scale wafer defect research center. The Center's research would be organized into three thrusts: bulk defects and imperfections, surface defects and imperfections, and cross-cutting areas such as metrology and simulation. The bulk defects and imperfections thrust would involve research on control of the nucleation, growth, motion and annihilation of silicon crystals. The surface defect thrust would investigate methods to control and engineer the wafer surface properties. The cross cutting areas thrust would focus on metrology development and fundamental knowledge underlying metrology tools. The Center would have Dr. George Rozgonyi of North Carolina State University and Ro bert Helms of Stanford University as co-Directors, and would involve researchers from the University of Arizona, Arizona State University, the University of South Florida, MIT, and Berkeley. There are currently six wafer manufacturing companies that are willing to pay $50,000 per year to be part of the Center. With the research expertise resident at the seven universities, this Center would aid the wafer suppliers in improving their silicon wafer quality, thus enabling them to better meet the market requirements of their customers, the silicon chip makers. The chip makers would then be able to product smaller, cheaper devices, making them more competitive in the electronics marketplace.