MRI: Acquisition of Chemical Mechanical Polishing System for Semiconductor Research

小行星9724387豪瑟 半导体行业的国家半导体技术路线图（NTRS）是基于平面硅集成电路制造技术的持续萎缩。 虽然NTRS预测，最终缩小到70纳米的栅极长度和4纳米的氧化层厚度在2010年将提供1 GHz的片上时钟频率和集成密度为0。9 x 108 cm-2用于微处理器，0. 64 X 1011 CM-2的DRAM，市场的需求将要求性能在未来几年继续提高，超过这些限制。 半导体工业和国防部最近都认识到了这一要求，并都在作出反应，敦促继续投资于研究，以实现这一更积极的目标。 NCSU的先进电子材料处理中心（AEMP）一直在国家科学基金会（NSF）通过ERC和半导体研究公司通过SEMATECH卓越中心以及现在的材料和批量处理研究计划的赞助下进行与此目标相关的前沿研究。 通过与半导体行业合作伙伴的合作，NCSU对行业的技术进步产生了相当大的影响。 最近，AEMP已经探索了与集成电路制造中使用垂直或第三维相关的问题，这与NTRS路线图不同。 通过这种方法可以显著地提高电路性能和功能电路密度。 因此，新的和更积极的研究目标已被确定，符合新的国家需要。 实现这些新目标的一个关键是在每个第三维加工步骤之后使表面平坦化和平滑化的能力。 对于这种工艺，化学机械抛光（CMP）是最佳解决方案。 该提案说明了这一能力的必要性，并要求提供资金购买设备，以便在阿富汗环境管理方案内建立这一能力。 请拨资金购买三个设备项目：（1）化学机械抛光工具，（2）化学机械抛光后使用的双面晶片清洁器，（3）原子力显微镜计量工具。 所有这三个项目都需要为未来的研究提供支持，研究CMP在硅IC制造工艺前端的应用。 ***

9724387 Hauser The semiconductor industry's National Technology Roadmap for Semiconductors (NTRS) is predicated on the continuing shrink of a planar silicon integrated circuit manufacturing technology. Although the NTRS forecasts that an ultimate shrink to 70 nm gate length and 4 nm oxide thickness in YEAR 2010 will provide on-chip clock frequencies of 1 Ghz and an integration density of 0. 9 x 108 cm-2 for microprocessors and 0. 64 X 1011CM-2 for DRAM, demands of the marketplace will require that performance continue to increase beyond these limits in future years. Both the semiconductor industry and the Department of Defense have recently recognized this requirement, and both are reacting to urge continued investment in research to achieve this more aggressive objective. NCSU's Advanced Electronic Materials Processing Center (AEMP) has been conducting leading edge research relevant to this objective under the sponsorship of both the National Science Foundation (NSF) through an ERC and the Semiconductor Research Corporation through a SEMATECH Center of Excellence and now a Materials and Bulk Processing Research program. Through collaboration with semiconductor industry partners, NCSU has made considerable impact on industry's technology advances. Recently, AEMP has explored the issues related to the use of the vertical or third dimension for integrated circuit fabrication, a departure from the NTRS roadmap. It may be possible by this approach to dramatically improve both circuit performance and functional circuit density. Thus, new and more aggressive research goals have been defined that are aligned with the new national need. One key to the accomplishment of these new goals is the ability to planarize and smooth the surface following each of the third dimension processing steps. For this process, chemical mechanical polishing (CMP) is the optimum solution. This proposal describes the need for this capability and requests funds for the purchase of equipment to establish this capability within the AEMP. Funds are requested for the purchase of three equipment items: (1) a chemical mechanical polishing tool, (2) a double sided wafer cleaner for use after CMP and, (3) an AFM metrology tool. All three items are needed to provide the support for future research looking at applications of CMP to front end of the line silicon IC manufacturing processes. ***