MRI: Acquisition of Chemical Mechanical Polishing System for Semiconductor Research

9724387 Hauser半导体行业的国家半导体技术路线图（NTRS）是基于平面硅集成电路制造技术的持续缩小。尽管NTRS预测，到2010年，栅极长度和氧化层厚度最终将缩小到70纳米，片上时钟频率将达到1 Ghz，集成密度为0。9 × 108 cm-2的微处理器和0。64 X 1011CM-2的DRAM，市场的需求将要求性能在未来几年继续超越这些限制。半导体行业和国防部最近都认识到了这一需求，双方都在做出反应，敦促继续投资研究，以实现这一更激进的目标。NCSU的先进电子材料加工中心（AEMP）一直在国家科学基金会（NSF）通过ERC和半导体研究公司通过SEMATECH卓越中心以及现在的材料和批量加工研究计划的赞助下开展与这一目标相关的前沿研究。通过与半导体行业合作伙伴的合作，NCSU对行业技术进步产生了相当大的影响。最近，AEMP探索了与垂直或三维集成电路制造相关的问题，这与NTRS路线图有所不同。这种方法有可能显著提高电路性能和功能电路密度。因此，新的和更积极的研究目标已经确定，与新的国家需要保持一致。实现这些新目标的一个关键是能够在每个三维处理步骤之后使表面平面化和光滑。对于该工艺，化学机械抛光（CMP）是最佳解决方案。该建议说明了对这种能力的需要，并要求为购买设备提供资金，以便在AEMP内建立这种能力。资金用于购买三个设备项目：(1)化学机械抛光工具，(2)CMP后使用的双面晶圆清洁器，(3)AFM计量工具。所有这三个项目都需要为未来研究CMP在前端硅集成电路制造工艺中的应用提供支持。＊＊＊

9724387 Hauser The semiconductor industry's National Technology Roadmap for Semiconductors (NTRS) is predicated on the continuing shrink of a planar silicon integrated circuit manufacturing technology. Although the NTRS forecasts that an ultimate shrink to 70 nm gate length and 4 nm oxide thickness in YEAR 2010 will provide on-chip clock frequencies of 1 Ghz and an integration density of 0. 9 x 108 cm-2 for microprocessors and 0. 64 X 1011CM-2 for DRAM, demands of the marketplace will require that performance continue to increase beyond these limits in future years. Both the semiconductor industry and the Department of Defense have recently recognized this requirement, and both are reacting to urge continued investment in research to achieve this more aggressive objective. NCSU's Advanced Electronic Materials Processing Center (AEMP) has been conducting leading edge research relevant to this objective under the sponsorship of both the National Science Foundation (NSF) through an ERC and the Semiconductor Research Corporation through a SEMATECH Center of Excellence and now a Materials and Bulk Processing Research program. Through collaboration with semiconductor industry partners, NCSU has made considerable impact on industry's technology advances. Recently, AEMP has explored the issues related to the use of the vertical or third dimension for integrated circuit fabrication, a departure from the NTRS roadmap. It may be possible by this approach to dramatically improve both circuit performance and functional circuit density. Thus, new and more aggressive research goals have been defined that are aligned with the new national need. One key to the accomplishment of these new goals is the ability to planarize and smooth the surface following each of the third dimension processing steps. For this process, chemical mechanical polishing (CMP) is the optimum solution. This proposal describes the need for this capability and requests funds for the purchase of equipment to establish this capability within the AEMP. Funds are requested for the purchase of three equipment items: (1) a chemical mechanical polishing tool, (2) a double sided wafer cleaner for use after CMP and, (3) an AFM metrology tool. All three items are needed to provide the support for future research looking at applications of CMP to front end of the line silicon IC manufacturing processes. ***