CAREER: Design Tools and Techniques for Analog Effects in Digital Integrated Circuits

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This research addresses the need to consider details of the analog behavior of digital circuits and interconnect in order to ensure correct functionality. Specifically it focuses on analysis of timing and noise in deep submicron circuit designs. All noise sources in a digital integrated circuit are being considered - coupled and ringing noise on signal lines, power supply noise, and noise from the circuits The effect of noise on delay is being considered in performance verification. Because many of the emerging timing and noise problems are associated with on-chip inductance, techniques for practically extracting on-chip inductance will be developed. The question of how the complex time-domain responses that result from inductive interconnect can be used in static timing and noise analysis is being investigated. Additional explorations are on using the complex time-domain responses that result from inductive interconnect for static timing and noise analysis. Other areas of investigation include a static solution to on-chip power grid integrity analysis and noise considerations in synthesis and circuit tuning. The educational plan includes building a VLSI CAD research laboratory, and development of courses in hardware design using FPGAs.