ITR: Asynchronous digital signal processing for the software radio

20世纪90年代见证了无线通信的爆炸式增长，如果不是革命性的，这在很大程度上是由数字处理能力的技术扩展推动的。第三代（3G）无线系统承诺更多的高比特率数据服务，如视频和互联网接入，使用宽带扩频调制。然而，尽管在未来十年内，0.1am以下的技术规模将继续带来好处，但这些移动3G系统将需要数字处理能力，以及可编程性和能源效率，这是传统数字设计技术无法实现的。实现数字中频和基带功能的可重构和灵活的软件无线电对于3G系统至关重要，因为需要支持多种调制波形和多种空中接口标准。这些系统预计需要1000 MIPS的数字中频处理功率和高达2000 MIPS的基带DSP功率。为了实现移动系统所需的功率水平，必须实现优于0.15 mW/MIPS的能效，同时提供3000 MIPS的处理能力，这比目前传统设计实践所能实现的要好一个数量级。在这项为期三年的广泛研究工作中，我们将考虑异步设计技术，以实现3G无线应用的节能，高性能数字信号处理。我们将充分利用异步设计固有的高性能和低功耗特性，仅在需要时消耗功率，并“适应”实际数据输入。具体来说，我们将细粒度异步微管道与自适应（或可编程）电源控制和数据流驱动的微架构相结合，在复杂的可编程数字信号处理能力和能源效率方面提供根本性的飞跃，这是现有同步技术无法实现的。我们打算开发一种异步可编程DSP，能够在软件中支持大部分is -95和W-CDMA标准，包括性能和功率密集型I和Q调制和解调，峰值功耗低于400 mW。

The 1990's have witnessed explosive, if not revolutionary, growth in wireless telecommunications, fueled in large measure by the technology scaling of digital processing power. Third-generation (3G) wire-less systems promise even more with high-bit-rate data services, such as video and Internet access, with wide-band spread-spectrum modulation. Yet, despite the continued benefit of technology scaling below0.1am in the next decade, these mobile 3G systems will demand digital processing power, along with programmability and energy efficiency, which are not achievable with conventional digital design techniques. Reconfigurable and flexible software radios, which implement digital IF as well as baseband function, will be essential for 3G systems because of the need to support multiple modulation waveforms and multiple air interface standards. These systems can be expected to demand 1000 MIPS of digital IF-processingpower and up to 2000 MIPS of baseband DSP power. To achieve power levels necessary for mobile sys-tem, energy efficiency of better than 0.15 mW/MIPS while deliever 3000 MIPS of processing power will be necessary, an order of magnitude better than what can be achieve today with conventional design practices. In this extensive three-year research effort, we will consider asynchronous design techniques for achievingenergy-efficient, high-performance digital signal processing for 3G wireless applications. We will fully exploit the inherent high-performance and low-power properties of asynchronous design, to consume power only where needed and to "adapt" to the actual data inputs. Specifically, we will combine fine-grained asynchronous micropipelines with adaptive (or programmable) power-supply control and a dataflow-driven microarchitecture to provide a funcadmental leap in complex programmable digital signal processing power and energy efficiency, unachievable using existing synchronous techniques. We in-tend to develop an asynchronous programmable DSP that is capable of supporting a significant fraction of the IS-95 and W-CDMA standards in software, including the performance- and power-intensive I and Q modulation and demodulation at less than 400 mW of peak power dissipation.