ITR: Asynchronous digital signal processing for the software radio

点击翻译按钮获取中文摘要

The 1990's have witnessed explosive, if not revolutionary, growth in wireless telecommunications, fueled in large measure by the technology scaling of digital processing power. Third-generation (3G) wire-less systems promise even more with high-bit-rate data services, such as video and Internet access, with wide-band spread-spectrum modulation. Yet, despite the continued benefit of technology scaling below0.1am in the next decade, these mobile 3G systems will demand digital processing power, along with programmability and energy efficiency, which are not achievable with conventional digital design techniques. Reconfigurable and flexible software radios, which implement digital IF as well as baseband function, will be essential for 3G systems because of the need to support multiple modulation waveforms and multiple air interface standards. These systems can be expected to demand 1000 MIPS of digital IF-processingpower and up to 2000 MIPS of baseband DSP power. To achieve power levels necessary for mobile sys-tem, energy efficiency of better than 0.15 mW/MIPS while deliever 3000 MIPS of processing power will be necessary, an order of magnitude better than what can be achieve today with conventional design practices. In this extensive three-year research effort, we will consider asynchronous design techniques for achievingenergy-efficient, high-performance digital signal processing for 3G wireless applications. We will fully exploit the inherent high-performance and low-power properties of asynchronous design, to consume power only where needed and to "adapt" to the actual data inputs. Specifically, we will combine fine-grained asynchronous micropipelines with adaptive (or programmable) power-supply control and a dataflow-driven microarchitecture to provide a funcadmental leap in complex programmable digital signal processing power and energy efficiency, unachievable using existing synchronous techniques. We in-tend to develop an asynchronous programmable DSP that is capable of supporting a significant fraction of the IS-95 and W-CDMA standards in software, including the performance- and power-intensive I and Q modulation and demodulation at less than 400 mW of peak power dissipation.