Methodologies and CAD Tools for the Design of Asynchronous Systems

随着设计人员在未来芯片设计中面临越来越多的挑战，异步（或无时钟）数字设计重新成为人们关注的焦点。这些电路承诺三个重要的好处：高性能，可扩展性和设计重用，以及低功耗。 本计画研究异步系统设计中的两个基本问题：（1）高速管线及管线化资料路径单元（加法器、乘法器等）的设计;以及（2）用于分布式控制的综合和优化的计算机辅助设计（CAD）算法和工具。 正在设计多千兆赫兹异步流水线，其中级仅与它们的邻居通信，并且在本地应用定时优化。 使用这种方法，大量的流水线数据路径组件（加法器/乘法器）正在设计，布局和评估。 用于异步分布式控制的CAD工具也正在开发中，使用新的自下而上（聚类）和自上而下（分区）算法。

Asynchronous (or clockless) digital design is the focus of renewed interest, as designers face increasing challenges in future chip design. These circuits promise three important benefits: high performance, scalability and design reuse, and low power. This project is investigating two basic problems in asynchronous system design: (1) design of high-speed pipelines and pipelined datapath units (adders, multipliers, etc.), and (2) computer-aided design (CAD) algorithms and tools for the synthesis and optimization of distributed control. Multi-Giga Hertz asynchronous pipelines are being designed, where stages only communicate with their neighbors, and where timing optimizations are applied locally. Using this approach, a substantial pipelined datapath component (adder/multiplier) is being designed, laid out and evaluated. CAD tools for asynchronous distributed control are also being developed, using new bottom-up (clustering) and top-down (partitioning) algorithms.