ITR: A CAD Framework for the Design and Optimization of Large-Scale Asynchronous Digital Systems

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Asynchronous (or clockless) circuits have become the focus of renewed interest because of their potential to alleviate a number of challenging problems in future-generation chip design: clock distribution, power management, and design reuse. To overcome the limitations of current asynchronous design methodologies, this project is developing an automated CAD framework for the synthesis and optimization of large-scale asynchronous systems. In addition to basic high-level scheduling, binding and allocation, and Hardware Description Language support (Verilog HDL), the project is exploring the open and challenging problems of: (a) high-performance pipeline synthesis and optimization; (b) architectural exploration (targeted to the frequent common-case operations); (c) distributed controller synthesis and optimization; (d) system-level performance and power analysis; and (e) the synthesis of mixed asynchronous/synchronous systems. The tool framework is being applied to a number of commercial examples and validated through chip design, fabrication, and test.