SHF: Small: An Asynchronous Network-on-Chip Methodology for Cost-Effective and Fault-Tolerant Heterogeneous SoC Architectures

SHF：小型：一种用于经济高效且容错的异构 SoC 架构的异步片上网络方法

• 批准号: 1527796
• 负责人: Steven Nowick
• 金额: $ 42万
• 依托单位: Columbia University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2019-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1527796&HistoricalAwards=false
• 关键词: SHF; Small; Asynchronous; Network; Chip

One of the grand challenges of the next decade is to provide cost-effective and systematic approaches to build large-scale computing systems to meet the country's future technological needs. Such systems will involve 100s or 1000s of processors, or more, on a single computer chip, which perform massively parallel computation tasks, and can be housed in either large data centers or even in desktop or hand-held consumer products. Such parallel computing is the key to supporting the continued growth of social networks (texting, Facebook) and rapid Web queries, as well as solving massive scientific computation problems, such as for weather, oceanography, air traffic control, military, and security. However, there are currently severe cost overheads in designing such systems: huge energy usage, thermal overheating, poor delivered performance, and complexity in assembling such complex and varied components into a single chip. Many of these bottlenecks have been exacerbated by the traditional use of a fixed-rate clock, which centrally controls all components on a chip. The goal of this research is to explore and significantly advance one highly promising alternative solution: to build ?plug-and-play? easy-to-assemble computer systems without any global clock, but instead through asynchronous (i.e. clock-less) assembly. Such a solution promises much lower energy consumption, and ease of assembly, of such systems. The project will also train students in asynchronous circuit design and the general area of information and computing technologies.The particular focus of this research is to develop structured digital interconnection networks for a chip, called "networks-on-chip", which form the "backbone" of recent commercial parallel computer systems. While initial solutions with asynchronous design have been promising, they have lacked fundamental features needed to make them viable for industry. In this proposal, several key features are developed for asynchronous networks-on-chip: error detection and correction, performance enhancement, and automated design flow. The approach will also be applied to a realistic cell phone application, to demonstrate the ease-of-design and cost benefits. Taken together, this new approach promises a significant advance forward in providing the capability to assemble complex parallel computer systems needed in the future.

下一个十年的重大挑战之一是提供具有成本效益和系统性的方法来构建大规模计算系统，以满足国家未来的技术需求。 这样的系统将在单个计算机芯片上包含数百或数千个处理器，这些处理器执行大规模并行计算任务，并且可以安装在大型数据中心甚至台式机或手持消费产品中。 这种并行计算是支持社交网络（短信，Facebook）和快速Web查询持续增长的关键，也是解决大规模科学计算问题的关键，例如天气，海洋学，空中交通管制，军事和安全。 然而，目前在设计这样的系统时存在严重的成本开销：巨大的能量使用、过热、差的交付性能，以及将这样复杂和多样的组件组装到单个芯片中的复杂性。 传统上使用固定速率时钟，集中控制芯片上的所有组件，这加剧了许多瓶颈。 这项研究的目标是探索和显着推进一个非常有前途的替代解决方案：建立？即插即用易于组装的计算机系统，没有任何全局时钟，而是通过异步（即无时钟）组装。 这样的解决方案保证了这样的系统的低得多的能量消耗和易于组装。该项目还将培训学生异步电路设计和信息和计算技术的一般领域，这项研究的特别重点是为芯片开发结构化数字互连网络，称为“芯片上网络”，这构成了最近商业并行计算机系统的“骨干”。 虽然异步设计的初始解决方案很有前途，但它们缺乏使其在工业上可行所需的基本功能。 在这个建议中，几个关键功能开发的异步片上网络：错误检测和纠正，性能增强，自动化设计流程。 该方法也将被应用到一个现实的手机应用程序，以证明易于设计和成本效益。 总之，这种新的方法有望在提供组装未来所需的复杂并行计算机系统的能力方面取得重大进展。