SHF:Small:Designing Low-Latency and Robust Interconnection Networks with Fine-Grain Dynamic Adaptivity Using Asynchronous Techniques

复杂异构数字系统的组织是未来十年甚至更长时间的基本研究问题之一。最近一个很有前途的策略是以互连网络或片上网络（noc）的形式使用结构化通信。这种noc最近已经在许多系统中使用，从用于消费者应用的嵌入式片上系统到用于高端并行处理器的内存接口。在同步（即时钟）noc的设计和能力方面已经取得了许多进展，但是对支持设计重用、混合时钟域和动态电压和频率缩放（DVFS，以提高系统功率）的需求增加，突出了单时钟框架的固有刚性。虽然已经开发了许多异步和全局异步本地同步（GALS） noc，并且在某些成本指标上显示出优势，但大多数noc具有主要的性能和面积开销，并且在一系列关键应用中没有竞争力，而其他旨在高性能的noc则需要使用先进的电路技术。该提案旨在弥合差距，开发中高端异步/GALS noc，主要使用标准硬件组件，与可比的单时钟设计相比，具有显著改善的成本指标：动态功耗、系统延迟、吞吐量、面积和可靠性。该方法的新颖之处在于探索在单个路由器节点级别使用细粒度动态自适应，其中，节点可以根据观察到的环境流量重新配置自己以“清除”延迟，吞吐量和静态功率方面的改进。将与最先进的时钟系统进行直接比较，使用有前途的多同步方法（具有单一时钟速率，但允许相位失调，称为“中同步”）。还将开发详细的模拟和综合工具和支持流程。所提出的框架的更广泛的影响将是在克服关键系统瓶颈方面为异步设计的竞争可行性提供一个新的进步水平。预计这项工作将通过使用异步在组织复杂系统方面发挥推动范式转变的作用。研究结果也有望在设计下一代noc方面取得重大进展。

The organization of complex heterogeneous digital systems looms as one of the fundamental research problems of the next decade and beyond. One recent promising strategy is the use of structured communication, in the form of interconnection networks or networks-on-chip (NoCs). Such NoCs have been recently used in many systems, ranging from embedded systems-on-chip for consumer applications to memory interfaces for high-end parallel processors. A number of advances have been made in the design and capabilities of synchronous (i.e. clocked) NoCs, but the increased need to support design reuse, mixed clock domains, and dynamic voltage and frequency scaling (DVFS, to improve system power), have highlighted the inherent rigidity of a single-clock framework. While a number of asynchronous and globally-asynchronous locally-synchronous (GALS) NoCs have been developed, and demonstrated benefits in some cost metrics, most have major performance and area overheads and are not competitive for a range of critical applications, while others aiming at high performance require the use of advanced circuit techniques. This proposal aims to bridge the gap, developing medium- to high-end asynchronous/GALS NoCs, using mostly standard hardware components, with significantly improved cost metrics over comparable single-clock designs: dynamic power, system latency, throughput, area and reliability. A novelty of the approach will be to explore the use of fine-grain dynamic adaptivity, at the individual router node level, where, opportunistically, nodes can reconfigure themselves to ``scavenge'' improvements in latency, throughput and static power, based on observed ambient traffic. A direct comparison will be made with state-of-the-art clocked systems, using a promising multi-synchronous approach (with a single clock rate, but tolerating phase misalignment, called ``mesochronous''). Detailed simulation and synthesis tools and support flows will also be developed.The broader impact of the proposed framework will be to provide a new level of advancement for the competitive viability of asynchronous design in overcoming key system bottlenecks. It is anticipated that this work will play a role in advancing a paradigm shift in organizing complex systems, through use of asynchrony. The results are also expected to provide a major advance in designing next-generation NoCs.