High-Performance and Low-Power Asynchronous Datapaths: Design and Applications

高性能和低功耗异步数据路径：设计和应用

• 批准号: 9734803
• 负责人: Steven Nowick
• 金额: $ 34万
• 依托单位: Columbia University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1998
• 资助国家: 美国
• 起止时间: 1998-07-15 至 2002-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9734803&HistoricalAwards=false
• 关键词: Performance; Low; Power; Asynchronous; Datapaths

This research is on asynchronous, or self-timed, design. Such designs eliminate the global synchronizing clock, thus permitting higher performance, scalability, and lower power. The project is investigating problems in datapath design: (1) the design of high-performance and low-power datapath components, and (2) a system-level application to compressed- code embedded processors. In (1), a technique, "speculative completion", for designing asynchronous datapath components which give high performance, yet have little area and power overhead is being developed. This technique allows use of existing synchronous components, with small amounts of added circuitry and a multi-slotted completion signal, to allow early completion. As part of this research, (a) the technique is being applied to design fast adders, multipliers, and comparators; and (b) new optimizations are being developed, which target statistically-skewed (i.e. non- random) input data that appear in real-world applications. In (2), research activity being carried out is focused on a system-level application: the design of embedded systems with compressed memories. The investigation includes (a) exploration and evaluation of a variety of memory compression techniques; (b) design of a small and fast asynchronous decompression circuit, which can decompress such memories, on the fly, at acceptable rates.

这项研究是关于异步或自定时设计的。 这种设计消除了全局同步时钟，从而允许更高的性能、可扩展性和更低的功耗。 本计画研究资料通路设计中的问题：（1）高效能与低功率资料通路元件的设计，以及（2）压缩编码嵌入式处理器的系统层级应用。在（1）中，正在开发一种用于设计异步数据路径组件的技术，“推测完成”，该异步数据路径组件提供高性能，而具有小的面积和功率开销。该技术允许使用现有的同步组件，具有少量的附加电路和多时隙完成信号，以允许早期完成。作为该研究的一部分，（a）该技术正被应用于设计快速加法器、乘法器和比较器;以及（B）新的优化正在被开发，其目标是出现在现实世界应用中的非随机偏斜（即，非随机）输入数据。 在（2）中，正在进行的研究活动集中在系统级应用：具有压缩存储器的嵌入式系统的设计。调查包括（a）各种存储器压缩技术的探索和评估;（B）一个小而快速的异步解压缩电路的设计，它可以在飞行中，在可接受的速率，这样的存储器。